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부품번호 74ACTQ244 기능
기능 Octal Buffer/Line Driver
제조업체 Fairchild Semiconductor
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74ACTQ244 데이터시트, 핀배열, 회로
March 2007
74ACQ244, 74ACTQ244
Quiet Series™ Octal Buffer/Line Driver with 3-STATE
tm
Outputs
Features
ICC and IOZ reduced by 50%
Guaranteed simultaneous switching noise level and
dynamic threshold performance
Guaranteed pin-to-pin skew AC performance
Improved latch-up immunity
3-STATE outputs drive bus lines or buffer memory
address registers
Outputs source/sink 24mA
Faster prop delays than the standard AC/ACT244
General Description
The ACQ/ACTQ244 is an octal buffer and line driver
designed to be employed as a memory address driver,
clock driver and bus oriented transmitter or receiver
which provides improved PC board density. The ACQ/
ACTQ utilizes Fairchild Quiet Series™ technology to
guarantee quiet output switching and improved dynamic
threshold performance. FACT Quiet Series™ features
GTO™ output control and undershoot corrector in addi-
tion to a split ground bus for superior performance.
Ordering Information
Package
Order Number Number
Package Description
74ACQ244SC
74ACQ244SJ
74ACTQ244SC
M20B
M20D
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
Body
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
Body
74ACTQ244SJ
74ACTQ244QSC
74ACTQ244MSA
M20D
MQA20
MSA20
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150” Wide
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
Connection Diagram
Pin Description
Pin Names
Description
OE1, OE2
I0–I 7
O0–O 7
3-STATE Output Enable Inputs
Inputs
Outputs
FACT™, Quiet Series™, FACT Quiet Series™, and GTO™ are trademarks of Fairchild Semiconductor Corporation.
©1989 Fairchild Semiconductor Corporation
74ACQ244, 74ACTQ244 Rev. 1.3
www.fairchildsemi.com




74ACTQ244 pdf, 반도체, 판매, 대치품
DC Electrical Characteristics for ACQ
Symbol
Parameter
VIH Minimum HIGH Level
Input Voltage
VIL Maximum LOW Level
Input Voltage
VOH Minimum HIGH Level
Output Voltage
VOL Maximum LOW Level
Output Voltage
IIN(3)
IOLD
IOHD
ICC(3)
IOZ
Maximum Input
Leakage Current
Minimum Dynamic
Output Current(2)
Maximum Quiescent
Supply Current
Maximum 3-STATE
Leakage Current
VOLP
VOLV
VIHD
VILD
Quiet Output Maximum
Dynamic VOL
Quiet Output Minimum
Dynamic VOL
Minimum HIGH Level
Dynamic Input Voltage
Maximum LOW Level
Dynamic Input Voltage
VCC (V) Conditions
3.0 VOUT = 0.1V or
4.5 VCC – 0.1V
5.5
3.0 VOUT = 0.1V or
4.5 VCC – 0.1V
5.5
3.0 IOUT = –50µA
4.5
5.5
VIN = VIL or VIH:
3.0 IOH = –12mA
4.5 IOH = –24mA
5.5 IOH = –24mA(1)
3.0 IOUT = 50µA
4.5
5.5
VIN = VIL or VIH:
3.0 IOL = 12mA
4.5 IOL = 24mA
5.5 IOL = 24mA(1)
5.5 VI = VCC, GND
TA = +25°C TA = –40°C to +85°C
Typ.
Guaranteed Limits
Units
1.5 2.1
2.1
V
2.25 3.15
3.15
2.75 3.85
3.85
1.5 0.9
0.9
V
2.25 1.35
1.35
2.75 1.65
1.65
2.99 2.9
2.9
V
4.49 4.4
4.4
5.49 5.4
5.4
0.002
0.001
0.001
2.56
3.86
4.86
0.1
0.1
0.1
2.46
3.76
4.76
0.1
0.1
0.1
V
0.36
0.36
0.36
±0.1
0.44
0.44
0.44
±1.0
µA
5.5 VOLD = 1.65V Max.
5.5 VOHD = 3.85V Min.
5.5 VIN = VCC or GND
4.0
75
–75
40.0
mA
mA
µA
5.5 VI (OE) = VIL, VIH;
VI = VCC, GND;
±0.25
VO = VCC, GND
5.0 Figures 1 & 2(4)
1.1 1.5
±2.5
µA
V
5.0 Figures 1 & 2(4)
–0.6 –1.2
V
5.0 (5)
3.1 3.5
V
5.0 (5)
1.9 1.5
V
Notes:
1. All outputs loaded thresholds on input associated with output under test.
2. Maximum test duration 2.0ms, one output loaded at a time.
3. IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC.
4. Max number of outputs defined as (n). Data Inputs are driven 0V to 5V. One output @ GND.
5. Max number of Data Inputs (n) switching. (n – 1) Inputs switching 0V to 5V (ACQ). Input-under-test switching:
5V to threshold (VILD), 0V to threshold (VIHD), f = 1MHz.
©1989 Fairchild Semiconductor Corporation
74ACQ244, 74ACTQ244 Rev. 1.3
4
www.fairchildsemi.com

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74ACTQ244 전자부품, 판매, 대치품
FACT Noise Characteristics
The setup of a noise characteristics measurement is crit-
ical to the accuracy and repeatability of the tests. The
following is a brief description of the setup used to mea-
sure the noise characteristics of FACT.
Equipment:
Hewlett Packard Model 8180A Word Generator
PC-163A Test Fixture
Tektronics Model 7854 Oscilloscope
Procedure:
1. Verify Test Fixture Loading: Standard Load 50pF,
500.
2. Deskew the HFS generator so that no two channels
have greater than 150ps skew between them. This
requires that the oscilloscope be deskewed first. It is
important to deskew the HFS generator channels
before testing. This will ensure that the outputs switch
simultaneously.
3. Terminate all inputs and outputs to ensure proper
loading of the outputs and that the input levels are at
the correct voltage.
4. Set the HFS generator to toggle all but one output at
a frequency of 1MHz. Greater frequencies will
increase DUT heating and effect the results of the
measurement.
5. Set the HFS generator input levels at 0V LOW and 3V
HIGH for ACT devices and 0V LOW and 5V HIGH for
AC devices. Verify levels with an oscilloscope.
VOLP/VOLV and VOHP/V OHV:
Determine the quiet output pin that demonstrates the
greatest noise levels. The worst case pin will usually
be the furthest from the ground pin. Monitor the output
voltages using a 50coaxial cable plugged into a
standard SMB type connector on the test fixture. Do
not use an active FET probe.
Measure VOLP and VOLV on the quiet output during
the worst case active and enable transition. Measure
VOHP and VOHV on the quiet output during the worst
case active and enable transition.
Verify that the GND reference recorded on the
oscilloscope has not drifted to ensure the accuracy
and repeatability of the measurements.
VILD and VIHD:
Monitor one of the switching outputs using a 50
coaxial cable plugged into a standard SMB type
connector on the test fixture. Do not use an active
FET probe.
First increase the input LOW voltage level, VIL, until
the output begins to oscillate or steps out a min of 2ns.
Oscillation is defined as noise on the output LOW
level that exceeds VIL limits, or on output HIGH levels
that exceed VIH limits. The input LOW voltage level at
which oscillation occurs is defined as VILD.
Next decrease the input HIGH voltage level, VIH, until
the output begins to oscillate or steps out a min of 2ns.
Oscillation is defined as noise on the output LOW
level that exceeds VIL limits, or on output HIGH levels
that exceed VIH limits. The input HIGH voltage level at
which oscillation occurs is defined as VIHD.
Verify that the GND reference recorded on the
oscilloscope has not drifted to ensure the accuracy
and repeatability of the measurements.
Notes:
14. VOHV and VOLP are measured with respect to ground
reference.
15. Input pulses have the following characteristics:
f = 1MHz, tr = 3ns, tf = 3ns, skew < 150ps.
Figure 1. Quiet Output Noise Voltage Waveforms
Figure 2. Simultaneous Switching Test Circuit
©1989 Fairchild Semiconductor Corporation
74ACQ244, 74ACTQ244 Rev. 1.3
7
www.fairchildsemi.com

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