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기능 Quiet Series Octal D-Type Flip-Flop with 3-STATE Outputs
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74ACTQ374SJ 데이터시트, 핀배열, 회로
April 2007
74ACQ374, 74ACTQ374
Quiet Series™ Octal D-Type Flip-Flop with 3-STATE
tm
Outputs
Features
ICC and IOZ reduced by 50%
Guaranteed simultaneous switching noise level and
dynamic threshold performance
Guaranteed pin-to-pin skew AC performance
Improved latch-up immunity
Buffered positive edge-triggered clock
3-STATE outputs drive bus lines or buffer memory
address registers
Outputs source/sink 24mA
Faster prop delays than the standard AC/ACT374
General Description
The ACQ/ACTQ374 is a high-speed, low-power octal
D-type flip-flop featuring separate D-type inputs for each
flip-flop and 3-STATE outputs for bus-oriented applica-
tions. A buffered Clock (CP) and Output Enable (OE) are
common to all flip-flops.
The ACQ/ACTQ374 utilizes FACT Quiet Series™ tech-
nology to guarantee quiet output switching and improve
dynamic threshold performance. FACT Quiet Series fea-
tures GTO™ output control and undershoot corrector in
addition to a split ground bus for superior performance.
www.DataSheet4U.com
Ordering Information
Package
Order Number Number
Package Description
74ACQ374SC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
Body
74ACQ374SJ
74ACTQ374SC
M20D
M20B
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
Body
74ACTQ374SJ
74ACTQ374QSC
M20D
MQA20
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
Connection Diagram
Pin Description
Pin Names
D0–D7
CP
OE
O0–O7
Description
Data Inputs
Clock Pulse Input
3-STATE Output Enable Input
3-STATE Outputs
FACT™, Quiet Series™, FACT Quiet Series™, and GTO™ are trademarks of Fairchild Semiconductor Corporation.
©1989 Fairchild Semiconductor Corporation
74ACQ374, 74ACTQ374 Rev. 1.3
www.fairchildsemi.com




74ACTQ374SJ pdf, 반도체, 판매, 대치품
DC Electrical Characteristics for ACQ
Symbol
Parameter
VIH Minimum HIGH Level
Input Voltage
VIL Maximum LOW Level
Input Voltage
VOH Minimum HIGH Level
Output Voltage
VOL Maximum LOW Level
Output Voltage
IIN(3)
IOLD
IOHD
ICC(3)
IOZ
Maximum Input
Leakage Current
Minimum Dynamic
Output Current(2)
Maximum Quiescent
Supply Current
Maximum 3-STATE
Leakage Current
VOLP
VOLV
VIHD
VILD
Quiet Output Maximum
Dynamic VOL
Quiet Output Minimum
Dynamic VOL
Minimum HIGH Level
Dynamic Input Voltage
Maximum LOW Level
Dynamic Input Voltage
VCC (V) Conditions
3.0 VOUT = 0.1V or
4.5 VCC – 0.1V
5.5
3.0 VOUT = 0.1V or
4.5 VCC – 0.1V
5.5
3.0 IOUT = –50µA
4.5
5.5
VIN = VIL or VIH:
3.0 IOH = –12mA
4.5 IOH = –24mA
5.5 IOH = –24mA(1)
3.0 IOUT = 50µA
4.5
5.5
3.0 IOL = 12mA
4.5 IOL = 24mA
5.5 IOL = 24mA(1)
5.5 VI = VCC, GND
5.5 VOLD = 1.65V Max.
5.5 VOHD = 3.85V Min.
5.5 VIN = VCC or GND
5.5 VI (OE) = VIL, VIH;
VI = VCC, GND;
VO = VCC, GND
5.0 Figures 1 & 2(4)
5.0 Figures 1 & 2(4)
5.0 (5)
5.0 (5)
TA = +25°C TA = –40°C to +85°C
Typ.
Guaranteed Limits
Units
1.5 2.1
2.1
V
2.25 3.15
3.15
2.75 3.85
3.85
1.5 0.9
0.9
V
2.25 1.35
1.35
2.75 1.65
1.65
2.99 2.9
2.9
V
4.49 4.4
4.4
5.49 5.4
5.4
0.002
0.001
0.001
2.56
3.86
4.86
0.1
0.1
0.1
0.36
0.36
0.36
±0.1
4.0
±0.25
2.46
3.76
4.76
0.1
0.1
0.1
0.44
0.44
0.44
±1.0
75
–75
40.0
±2.5
V
µA
mA
mA
µA
µA
1.1 1.5
–0.6 –1.2
3.1 3.5
1.9 1.5
V
V
V
V
Notes:
1. All outputs loaded; thresholds on input associated with output under test.
2. Maximum test duration 2.0ms, one output loaded at a time.
3. IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC.
4. Max number of outputs defined as (n). Data inputs are driven 0V to 5V. One output @ GND.
5. Max number of data inputs (n) switching. (n–1) inputs switching 0V to 5V (ACQ). Input-under-test switching:
5V to threshold (VILD), 0V to threshold (VIHD), f = 1MHz.
©1989 Fairchild Semiconductor Corporation
74ACQ374, 74ACTQ374 Rev. 1.3
4
www.fairchildsemi.com

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74ACTQ374SJ 전자부품, 판매, 대치품
AC Electrical Characteristics for ACTQ
Symbol
fMAX
Parameter
Maximum Clock
Frequency
VCC (V)(13)
5.0
TA = +25°C,
CL = 50pF
Min. Typ. Max.
85
TA = –40°C to +85°C,
CL = 50pF
Min.
Max.
80
Units
MHz
tPLH, tPHL Propagation Delay,
CP to On
5.0 2.0 7.0 9.0 2.0
tPZL, tPZH Output Enable Time
5.0 2.0 7.5 9.0 2.0
tPHZ, tPLZ Output Disable Time
5.0
1.0 8.0 10.0
1.0
tOSHL, tOSLH Output to Output Skew,
CP to On(14)
5.0
0.5 1.0
9.5 ns
9.5 ns
10.5 ns
1.0 ns
Notes:
13. Voltage range 5.0 is 5.0V ± 0.5V.
14. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate
outputs of the same device. The specification applies to any outputs switching in the same direction, either
HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design.
AC Operating Requirements for ACTQ
Symbol
Parameter
tS Setup Time, HIGH or LOW,
Dn to CP
tH Hold Time, HIGH or LOW,
Dn to CP
tH CP Pulse Width, HIGH or LOW
Note:
15. Voltage range 5.0 is 5.0V ± 0.5V
VCC (V)(15)
5.0
5.0
5.0
TA = +25°C,
CL = 50pF
TA = –40°C to +85°C,
CL = 50pF
Typ. Guaranteed Minimum
0 3.0
3.0
0 1.5
1.5
2.0 4.0
4.0
Units
ns
ns
ns
Capacitance
Symbol
CIN
CPD
Parameter
Input Capacitance
Power Dissipation Capacitance
Conditions
VCC = OPEN
VCC = 5.0V
Typ.
4.5
42.0
Units
pF
pF
©1989 Fairchild Semiconductor Corporation
74ACQ374, 74ACTQ374 Rev. 1.3
7
www.fairchildsemi.com

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관련 데이터시트

부품번호상세설명 및 기능제조사
74ACTQ374SC

Quiet Series Octal D-Type Flip-Flop with 3-STATE Outputs

Fairchild Semiconductor
Fairchild Semiconductor
74ACTQ374SJ

Quiet Series Octal D-Type Flip-Flop with 3-STATE Outputs

Fairchild Semiconductor
Fairchild Semiconductor

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