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PDF 74ACTQ574PC Data sheet ( Hoja de datos )
| Número de pieza | 74ACTQ574PC | |
| Descripción | Quiet Series Octal D-Type Flip-Flop with 3-STATE Outputs | |
| Fabricantes | Fairchild Semiconductor | |
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January 1990
Revised November 1999
74ACQ574 • 74ACTQ574
Quiet Series Octal D-Type Flip-Flop
with 3-STATE Outputs
General Description
The ACQ/ACTQ574 is a high-speed, low-power octal D-
type flip-flop with a buffered Common Clock (CP) and a
buffered common Output Enable (OE). The information
presented to the D inputs is stored in the flip-flops on the
LOW-to-HIGH clock (CP) transition.
ACQ/ACTQ574 utilizes FACT Quiet Series technology to
guarantee quiet output switching and improve dynamic
threshold performance. FACT Quiet Series features GTO
output control and undershoot corrector in addition to a
split ground bus for superior performance.
The ACQ/ACTQ574 is functionally identical to the
ACTQ374 but with different pin-out.
Features
s ICC and IOZ reduced by 50%
s Guaranteed simultaneous switching noise level and
dynamic threshold performance
s Guaranteed pin-to-pin skew AC performance
s Inputs and outputs on opposite sides of the package
allowing easy interface with microprocessors
s Functionally identical to the ACQ/ACTQ374
s 3-STATE outputs drive bus lines or buffer memory
address registers
s Outputs source/sink 24 mA
s Faster prop delays than the standard AC/ACT574
Ordering Code:
Order Number Package Number
Package Description
74ACQ574SC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
74ACQ574SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACQ574PC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
74ACTQ574SC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
74ACTQ574SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACTQ574PC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names
D0–D7
CP
OE
O0–O7
Description
Data Inputs
Clock Pulse Input
3-STATE Output Enable Input
3-STATE Outputs
FACT, Quiet Series, FACT Quiet Series and GTO are trademarks of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation DS010634
www.fairchildsemi.com
1 page  
DC Electrical Characteristics for ACTQ (Continued)
Note 12: Max number of data inputs (n) switching. (n−1) inputs switching 0V to 3V (ACTQ). Input-under-test switching:
3V to threshold (VILD), 0V to threshold (VIHD), f = 1 MHz.
AC Electrical Characteristics for ACQ
VCC
TA = +25°C
TA = −40°C to +85°C
Symbol
Parameter
(V) CL = 50 pF
CL = 50 pF
Units
(Note 13)
Min
Typ
Max
Min
Max
fMAX
Maximum Clock
Frequency
3.3 75
5.0 90
70
MHz
85
tPLH Propagation Delay
tPHL
CP to On
tPZH Output Enable Time
tPZL
tPHZ Output Disable Time
tPLZ
tOSHL
Output to Output Skew (Note 14)
tOSLH
CP to On
Note 13: Voltage Range 5.0 is 5.0V ± 0.5V
3.3 3.0 9.5 13.0 3.0 13.5
5.0 2.0 6.5 8.5 2.0 9.0
3.3 3.0 9.5 13.0 3.0 13.5
5.0 2.0 6.5 8.5 2.0 9.0
3.3 1.0 9.5 14.5 1.0 15.0
5.0 1.0 8.0 9.5 1.0 10.0
3.3 1.0 1.5 1.5
5.0 0.5 1.0 1.0
ns
ns
ns
ns
Voltage Range 3.3 is 3.3V ± 0.3V
Note 14: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design.
AC Operating Requirements for ACQ
Symbol
Parameter
tS Setup Time, HIGH or LOW
Dn to CP
tH Hold Time, HIGH or LOW
Dn to CP
tW CP Pulse Width,
HIGH or LOW
Note 15: Voltage Range 5.0 is 5.0V ± 0.5V
Voltage Range 3.3 is 3.3V ± 0.3V
VCC
(V)
(Note 15)
3.3
5.0
3.3
5.0
3.3
5.0
TA = +25°C
TA = −40°C to +85°C
CL = 50 pF
CL = 50 pF
Typ Guaranteed Minimum
0 3.0
3.0
0 3.0
3.0
0 1.5
1.5
0 1.5
1.5
2.0 4.0
4.0
2.0 4.0
4.0
Units
ns
ns
ns
AC Electrical Characteristics for ACTQ
VCC
TA = +25°C
TA = −40°C to +85°C
Symbol
Parameter
(V) CL = 50 pF
CL = 50 pF
Units
(Note 16)
Min
Typ
Max
Min
Max
fMAX
Maximum Clock Frequency
tPLH Propagation Delay
tPHL
CP to On
tPZH Output Enable
tPZL Time
tPHZ Output Disable
tPLZ Time
tOSHL
Output to Output Skew (Note 17)
tOSLH
CP to On
Note 16: Voltage Range 5.0 is 5.0V ± 0.5V.
5.0 85
80 MHz
5.0 2.0 7.0 9.0 2.0 9.5 ns
5.0 2.0 7.0 9.0 2.0 9.5 ns
5.0 1.0 8.0 10.0 1.0 10.5 ns
5.0 0.5 1.0 1.0 ns
Note 17: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design.
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