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부품번호 | 74ACTQ841 기능 |
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기능 | Quiet Seriesa 10-Bit Transparent Latch with 3-STATE Outputs | ||
제조업체 | Fairchild Semiconductor | ||
로고 | |||
전체 7 페이지수
March 1990
Revised November 1998
74ACTQ841
Quiet Series™ 10-Bit Transparent Latch
with 3-STATE Outputs
General Description
The ACTQ841 bus interface latch is designed to eliminate
the extra packages required to buffer existing latches and
provide extra data width for wider address/data paths or
buses carrying parity. The 841 is a 10-bit transparent latch,
a 10-bit version of the 373. The ACTQ841 utilizes Fairchild
Quiet Series™ technology to guarantee quiet output switch-
ing and improved dynamic threshold performance. FACT
Quiet Series features GTO™ output control and undershoot
corrector in addition to a split ground bus for superior per-
formance.
Features
s Guaranteed simultaneous switching noise level and
dynamic threshold performance
s Guaranteed pin-to-pin skew AC performance
s Inputs and outputs on opposite sides of package allow
easy interface with microprocessors
s Improved latch-up immunity
s Outputs source/sink 24 mA
s Has TTL-compatible inputs
Ordering Code:
Order Number Package Number
Package Description
74ACTQ841SC
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
74ACTQ841SPC
N24C
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC, MS-100, 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
Pin Assignment
for DIP and SOIC
Pin Descriptions
Pin Names
D0–D9
O0–O9
OE
LE
Description
Data Inputs
3-STATE Outputs
Output Enable
Latch Enable
FACT™, Quiet Series™, FACT Quiet Series™ and GTO™ are trademarks of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation DS010688.prf
www.fairchildsemi.com
DC Electrical Characteristics (Continued)
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Note 4: PDIP package.
Note 5: Max number of outputs defined as (n). Data inputs are driven 0V to 3V. One output @ GND.
Note 6: Max number of data inputs (n) switching. (n − 1) inputs switching 0V to 3V (ACTQ). Input-under-test switching:
3V to threshold (VILD), 0V to threshold (VIHD), f = 1 MHz.
AC Electrical Characteristics
VCC
TA = +25°C
TA = −40°C to +85°C
Symbol
Parameter
(V) CL = 50 pF
CL = 50 pF
Units
(Note 7)
Min
Typ
Max
Min
Max
tPLH Propagation Delay
tPHL
Dn to On
tPLH Propagation Delay
tPHL
LE to On
tPZH Output Enable Time
tPZL OE to On
tPHZ
Output Disable Time
tPLZ OE to On
tOSLH
Output to Output
tOSHL
Skew Dn to On (Note 8)
Note 7: Voltage Range 5.0 is 5.0V ± 0.5V.
5.0 2.5 7.0 9.5 2.0 10.0
5.0 2.5 7.0 9.5 2.0 10.0
5.0 2.5 8.5 11.0 2.0 12.0
5.0 1.0 6.0 9.0 1.0 9.5
5.0 0.5 1.0 1.0
ns
ns
ns
ns
ns
Note 8: Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs within the same packaged device.
The specification applies to any outputs switching in the same direction, either HIGH to LOW (tOSHL) or LOW to HIGH (tOSLH). Parameter guaranteed by
design. Not tested.
AC Operating Requirements
Symbol
Parameter
tS Setup Time, HIGH or LOW
Dn to LE
tH Hold Time, HIGH or LOW
Dn to LE
tW LE Pulse Width, HIGH
Note 9: Voltage Range 5.0 is 5.0V ±0.5V.
VCC
(V)
(Note 9)
5.0
5.0
5.0
TA = + 25
TA = − 40°C to + 85°C
CL = 50 pF °C
CL = 50 pF
Typ Guaranteed Minimum
3.0 3.0
1.5 1.5
4.0 4.0
Units
ns
ns
ns
Capacitance
Symbol
CIN
CPD
Parameter
Input Capacitance
Power Dissipation Capacitance
Typ
4.5
85.0
Units
pF
pF
VCC = OPEN
VCC = 5.0V
Conditions
www.fairchildsemi.com
4
4페이지 Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300” Wide
Package Number N24C
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
Fairchild does not assumeany responsibility for use of any circuitry described, nocircuit patent licenses are impliedandFairchildreserves theright at any timewithout noticetochange saidcircuitry andspecifications.
7페이지 | |||
구 성 | 총 7 페이지수 | ||
다운로드 | [ 74ACTQ841.PDF 데이터시트 ] |
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부품번호 | 상세설명 및 기능 | 제조사 |
74ACTQ841 | Quiet Seriesa 10-Bit Transparent Latch with 3-STATE Outputs | Fairchild Semiconductor |
74ACTQ843 | Quiet Seriesa 9-Bit Transparent Latch with 3-STATE Outputs | Fairchild Semiconductor |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |