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PDF 74ACTQ843 Data sheet ( Hoja de datos )
| Número de pieza | 74ACTQ843 | |
| Descripción | Quiet Seriesa 9-Bit Transparent Latch with 3-STATE Outputs | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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March 1990
Revised December 1998
74ACTQ843
Quiet Series™ 9-Bit Transparent Latch
with 3-STATE Outputs
General Description
The ACTQ843 bus interface latch is designed to eliminate
the extra packages required to buffer existing latches and
provide extra data width for wider address/data paths. The
ACTQ843 utilizes Fairchild FACT Quiet Series™ technol-
ogy to guarantee quiet output switching and improved
dynamic threshold performance. FACT Quiet Series fea-
tures GTO™ output control and undershoot corrector in
addition to a split ground bus for superior performance.
Features
s Guaranteed simultaneous switching noise level and
dynamic threshold performance
s Guaranteed pin-to-pin skew AC performance
s Inputs and outputs on opposite sides of package for
easy interface with microprocessors
s Improved latch-up immunity
s Outputs source/sink 24 mA
s ACTQ843 has TTL-compatible inputs
s Functionally and pin-compatible to AMD’s AM29843
s 3-STATE outputs for bus interfacing
Ordering Code:
Order Number Package Number
Package Description
74ACTQ843SC
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
74ACTQ843SPC
N24C
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
Pin Assignment for DIP and SOIC
Pin Descriptions
Pin Names
D0–D8
O0–O8
OE
LE
CLR
PRE
Description
Data Inputs
Data Outputs
Output Enable
Latch Enable
Clear
Preset
FACT™, Quiet Series™, FACT Quiet Series™ and GTO™ are trademarks of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation DS010689.prf
www.fairchildsemi.com
1 page  
AC Operating Requirements
Symbol
Parameter
tS Setup Time, HIGH or LOW
Dn to LE
tH Hold Time, HIGH or LOW
Dn to LE
tW LE Pulse Width, HIGH
tW PRE Pulse Width, LOW
tW CLR Pulse Width, LOW
trec PRE Recovery Time
trec CLR Recovery Time
Note 9: Voltage Range 5.0 is 5.0V ±0.5V.
Capacitance
Symbol
CIN
CPD
Parameter
Input Capacitance
Power Dissipation Capacitance
VCC
(V)
(Note 9)
5.0
5.0
5.0
5.0
5.0
5.0
5.0
TA = +25°C
TA = −40°C to +85°C
CL = 50 pF
CL = 50 pF
Typ Guaranteed Minimum
3.0 3.0
1.5 1.5
4.0 4.0
4.0 4.0
4.0 4.0
2.0 2.0
2.0 2.0
Units
ns
ns
ns
ns
ns
ns
ns
Typ Units
Conditions
4.5 pF VCC = OPEN
52 pF VCC = 5.0V
5 www.fairchildsemi.com
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet 74ACTQ843.PDF ] | |
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