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PDF 74AHCT14 Data sheet ( Hoja de datos )

Número de pieza 74AHCT14
Descripción Hex inverting Schmitt trigger
Fabricantes NXP Semiconductors 
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No Preview Available ! 74AHCT14 Hoja de datos, Descripción, Manual

74AHC14; 74AHCT14
Hex inverting Schmitt trigger
Rev. 05 — 4 May 2009
Product data sheet
1. General description
The 74AHC14; 74AHCT14 is a high-speed Si-gate CMOS device and is pin compatible
with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard
No. 7A.
The 74AHC14; 74AHCT14 provides six inverting buffers with Schmitt-trigger action. They
are capable of transforming slowly changing input signals into sharply defined, jitter-free
output signals.
2. Features
I Balanced propagation delays
I All inputs have Schmitt-trigger actions
I Inputs accept voltages higher than VCC
I Input levels:
N For 74AHC14: CMOS level
N For 74AHCT14: TTL level
I ESD protection:
N HBM EIA/JESD22-A114E exceeds 2000 V
N MM EIA/JESD22-A115-A exceeds 200 V
N CDM EIA/JESD22-C101C exceeds 1000 V
I Multiple package options
I Specified from 40 °C to +85 °C and from 40 °C to +125 °C

1 page




74AHCT14 pdf
NXP Semiconductors
74AHC14; 74AHCT14
Hex inverting Schmitt trigger
9. Static characteristics
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions
25 °C
40 °C to +85 °C 40 °C to +125 °C Unit
Min Typ Max Min Max Min Max
74AHC14
VOH HIGH-level VI = VT+ or VT
output voltage IO = 50 µA; VCC = 2.0 V
1.9 2.0
-
1.9
-
1.9
-V
IO = 50 µA; VCC = 3.0 V 2.9 3.0 -
2.9
-
2.9
-V
IO = 50 µA; VCC = 4.5 V 4.4 4.5 -
4.4
-
4.4
-V
IO = 4.0 mA; VCC = 3.0 V 2.58 -
- 2.48
-
2.40
-V
IO = 8.0 mA; VCC = 4.5 V 3.94 -
- 3.80
-
3.70
-V
VOL LOW-level
VI = VT+ or VT
output voltage IO = 50 µA; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V
IO = 50 µA; VCC = 3.0 V - 0 0.1 - 0.1 - 0.1 V
IO = 50 µA; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V
IO = 4.0 mA; VCC = 3.0 V - - 0.36 - 0.44 - 0.55 V
IO = 8.0 mA; VCC = 4.5 V - - 0.36 - 0.44 - 0.55 V
II input leakage VI = 5.5 V or GND;
current
VCC = 0 V to 5.5 V
- - 0.1 - 1.0 - 2.0 µA
ICC supply current VI = VCC or GND; IO = 0 A; - - 2.0 - 20 - 40 µA
VCC = 5.5 V
CI input
capacitance
- 3 10
-
10
-
10 pF
CO output
capacitance
-4-
-
-
-
- pF
74AHCT14
VOH
VOL
II
ICC
ICC
CI
HIGH-level
VI = VT+ or VT
output voltage IO = 50 µA; VCC = 4.5 V
4.4 4.5
-
4.4
IO = 8.0 mA; VCC = 4.5 V 3.94 -
- 3.80
LOW-level
VI = VT+ or VT
output voltage IO = 50 µA; VCC = 4.5 V
- 0 0.1 -
IO = 8.0 mA; VCC = 4.5 V - - 0.36 -
input leakage VI = 5.5 V or GND;
current
VCC = 0 V to 5.5 V
- - 0.1 -
supply current VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
- - 2.0 -
additional
per input pin;
- - 1.35 -
supply current VI = VCC 2.1 V; other pins
at VCC or GND; IO = 0 A;
VCC = 4.5 V to 5.5 V
input
capacitance
- 3 10
-
-
-
0.1
0.44
1.0
20
1.5
10
4.4
3.70
-
-
-
-
-
-
-V
-V
0.1 V
0.55 V
2.0 µA
40 µA
1.5 mA
10 pF
CO output
capacitance
-4-
-
-
-
- pF
74AHC_AHCT14_5
Product data sheet
Rev. 05 — 4 May 2009
© NXP B.V. 2009. All rights reserved.
5 of 16

5 Page





74AHCT14 arduino
NXP Semiconductors
74AHC14; 74AHCT14
Hex inverting Schmitt trigger
15. Package outline
SO14: plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
y
Z
14
D
pin 1 index
1
e
EA
X
c
HE
vM A
8
A2
A1
7
bp
wM
Q
(A3)
A
Lp
L
detail X
θ
0 2.5 5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
UNIT max. A1 A2 A3 bp
c D(1) E(1) e
HE
L
Lp
Q
mm
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
8.75
8.55
4.0
3.8
1.27
6.2
5.8
1.05
1.0
0.4
0.7
0.6
inches
0.069
0.010
0.004
0.057
0.049
0.01
0.019 0.0100 0.35
0.014 0.0075 0.34
0.16
0.15
0.05
0.244
0.228
0.041
0.039
0.016
0.028
0.024
v
0.25
0.01
w y Z (1)
0.25 0.1
0.7
0.3
0.01
0.004
0.028
0.012
θ
8o
0o
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
OUTLINE
VERSION
SOT108-1
IEC
076E06
REFERENCES
JEDEC
JEITA
MS-012
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
Fig 13. Package outline SOT108-1 (SO14)
74AHC_AHCT14_5
Product data sheet
Rev. 05 — 4 May 2009
© NXP B.V. 2009. All rights reserved.
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