PDF 74ALVC16245 Data sheet ( Hoja de datos )

Número de pieza	74ALVC16245
Descripción	Low Voltage 16-Bit Bidirectional Transceiver with 3.6V Tolerant Inputs and Outputs
Fabricantes	Fairchild Semiconductor
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No Preview Available ! October 2001 Revised August 2002 74ALVC16245 Low Voltage 16-Bit Bidirectional Transceiver with 3.6V Tolerant Inputs and Outputs General Description The ALVC16245 contains sixteen non-inverting bidirec- tional buffers with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. Each byte has separate 3-STATE control inputs which can be shorted together for full 16-bit operation. The T/R inputs determine the direction of data flow through the device. The OE inputs disable both the A and B ports by placing them in a high impedance state. The 74ALVC16245 is designed for low voltage (1.65V to 3.6V) VCC applications with I/O compatibility up to 3.6V. The 74ALVC16245 is fabricated with an advanced CMOS technology to achieve high speed operation while maintain- ing low CMOS power dissipation. Features s 1.65V–3.6V VCC supply operation s 3.6V tolerant inputs and outputs s tPD 3.0 ns max for 3.0V to 3.6V VCC 3.5 ns max for 2.3V to 2.7V VCC 6.0 ns max for 1.65V to 1.95V VCC s Power-down high impedance inputs and outputs s Supports live insertion/withdrawal (Note 1) s Uses patented noise/EMI reduction circuitry s Latchup conforms to JEDEC JED78 s ESD performance: Human body model > 2000V Machine model >200V s Also packaged in plastic Fine-Pitch Ball Grid Array (FBGA) Note 1: To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pull-up resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver. Ordering Code: Order Number Package Number Package Description 74ALVC16245G (Note 2)(Note 3) BGA54A 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide 74ALVC16245MTD (Note 3) MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Note 2: Ordering code “G” indicates Trays. Note 3: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol © 2002 Fairchild Semiconductor Corporation DS500678 www.fairchildsemi.com 1 page AC Loading and Waveforms TABLE 1. Values for Figure 1 TEST tPLH, tPHL tPZL, tPLZ tPZH, tPHZ SWITCH Open VL GND FIGURE 1. AC Test Circuit TABLE 2. Variable Matrix (Input Characteristics: f = 1MHz; tr = tf = 2ns; ZO = 50Ω) Symbol Vmi Vmo VX VY VL 3.3V ± 0.3V 1.5V 1.5V VOL + 0.3V VOH − 0.3V 6V 2.7V 1.5V 1.5V VOL + 0.3V VOH − 0.3V 6V VCC 2.5 ± 0.2V VCC/2 VCC/2 VOL + 0.15V VOH − 0.15V VCC2 1.8V ± 0.15V VCC/2 VCC/2 VOL + 0.15V VOH − 0.15V VCC2 FIGURE 2. Waveform for Inverting and Non-inverting Functions FIGURE 3. 3-STATE Output High Enable and Disable Times for Low Voltage Logic FIGURE 4. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic 5 www.fairchildsemi.com 5 Page

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