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74ALVC162601T 데이터시트 PDF




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부품번호 74ALVC162601T 기능
기능 Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs and 26 Series Resistors in the B-Port Outputs
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74ALVC162601T 데이터시트, 핀배열, 회로
September 2001
Revised October 2001
74ALVC162601
Low Voltage 18-Bit Universal Bus Transceivers
with 3.6V Tolerant Inputs and Outputs
and 26Series Resistors in the B-Port Outputs
General Description
The 74ALVC162601, 18-bit universal bus transceiver, com-
bines D-type latches and D-type flip-flops to allow data flow
in transparent, latched, and clocked modes.
Data flow in each direction is controlled by output-enable
(OEAB and OEBA), latch-enable (LEAB and LEBA), and
clock (CLKAB and CLKBA) inputs. The clock can be con-
trolled by the clock-enable (CLKENAB and CLKENBA)
inputs. For A-to-B data flow, the device operates in the
transparent mode when LEAB is HIGH. When LEAB is
LOW, the A data is latched if CLKAB is held at a HIGH-to-
LOW logic level. If LEAB is LOW, the A bus data is stored
in the latch/flip-flop on the LOW-to-HIGH transition of
CLKAB. Output-enable OEAB is active-LOW. When OEAB
is HIGH, the outputs are in the HIGH-impedance state.
Data flow for B to A is similar to that of A to B but uses
OEBA, LEBA, CLKBA and CLKENBA.
The 74ALVC162601 is designed for low voltage (1.65V to
3.6V) VCC applications with I/O compatibility up to 3.6V.
The 74ALVC162601 is also designed with 26series
resistors in the B-Port outputs. This design reduces line
noise in applications such as memory address drivers,
clock drivers, and bus transceivers/transmitters.
Features
I 1.65V–3.6V VCC supply operation
I 3.6V tolerant inputs and outputs
I 26series resistors in B-Port outputs
I tPD (A to B)
4.3 ns max for 3.0V to 3.6V VCC
5.1 ns max for 2.3V to 2.7V VCC
9.2 ns max for 1.65V to 1.95V VCC
I Power-down high impedance inputs and outputs
I Supports live insertion/withdrawal (Note 1)
I Uses patented noise/EMI reduction circuitry
I Latchup conforms to JEDEC JED78
I ESD performance:
Human body model > 2000V
Machine model >200V
Note 1: To ensure the high-impedance state during power up or power
down, OE should be tied to VCC through a pull-up resistor; the minimum
value of the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Order Number
Package
Number
Package Description
74ALVC162601T
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter Xto the ordering code.
© 2001 Fairchild Semiconductor Corporation DS500676
www.fairchildsemi.com




74ALVC162601T pdf, 반도체, 판매, 대치품
DC Electrical Characteristics (Continued)
Symbol
Parameter
IOH High Level Output Current
A Outputs
Conditions
High Level Output Current
B Outputs
IOL Low Level Output Current
A Outputs
Low Level Output Current
B Outputs
II
IOZ
IOFF
ICC
ICC
Input Leakage Current
3-STATE Output Leakage
Power Off Leakage Current
Quiescent Supply Current
Increase in ICC per Input
0 VI 3.6V
0 VO 3.6V, VI = VIH or VIL
0V (VI, VO) 3.6V
VI = VCC or GND, IO = 0
VIH = VCC 0.6V
AC Electrical Characteristics
VCC
(V)
1.65
2.3
2.7
3.0
1.65
2.3
2.7
3.0
1.65
2.3
2.7
3
1.65
2.3
2.7
3.0
1.65 - 3.6
1.65 - 3.6
0
3.6
2.7 - 3.6
Min
Max Units
4
12
12
24
mA
2
6
8
12
4
12
12
24
mA
2
6
8
12
±5.0 µA
±10 µA
10 mA
40 µA
750 µA
Symbol
Parameter
fMAX
tPHL, tPLH
tPHL, tPLH
tPHL, tPLH
tPZL, tPZH
Maximum Clock Frequency
Propagation Delay
A to B
Propagation Delay
B to A
Propagation Delay
Clock to A
Propagation Delay
Clock to B
Propagation Delay
LEBA to A
Propagation Delay
LEAB to B
Output Enable Time
OEBA to A
Output Enable Time
OEAB to B
TA = −40°C to +85°C, RL = 500
CL = 50 pF
CL = 30 pF
VCC = 3.3V ± 0.3V
VCC = 2.7V
VCC = 2.5 ± 0.2V VCC = 1.8V ± 0.15V
Min Max Min Max Min Max Min Max
250 200 200 125
Units
MHz
1.3 4.3 1.5 5.1 1 4.6 1.5 9.2
ns
1.3 3.4 1.5 4.0 1 3.5 1.5 7.0
1.3 4.0 1.5 4.9 1.0 4.4 1.5 8.8
ns
1.3 4.9 1.5 6.0 1.0 5.5 1.5 9.8
1.3 4.0 1.5 4.9 1.0 4.4 1.5 8.8
ns
1.3 4.9 1.5 6.3 1.0 5.8 1.5 9.8
1.3 4.3 1.5 5.4 1.0 4.9 1.5 9.8
ns
1.3 4.8 1.5 6.4 1.0 5.9 1.5 9.8
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74ALVC162601T 전자부품, 판매, 대치품
Physical Dimensions inches (millimeters) unless otherwise noted
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD56
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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부품번호상세설명 및 기능제조사
74ALVC162601

Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs and 26 Series Resistors in the B-Port Outputs

Fairchild Semiconductor
Fairchild Semiconductor
74ALVC162601T

Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs and 26 Series Resistors in the B-Port Outputs

Fairchild Semiconductor
Fairchild Semiconductor

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