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74ALVC16601 데이터시트 PDF




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부품번호 74ALVC16601 기능
기능 Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs
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74ALVC16601 데이터시트, 핀배열, 회로
October 2001
Revised October 2001
74ALVC16601
Low Voltage 18-Bit Universal Bus Transceivers
with 3.6V Tolerant Inputs and Outputs
General Description
The ALVC16601 is an 18-bit universal bus transceiver
which combines D-type latches and D-type flip-flops to
allow data flow in transparent, latched, and clocked modes.
Data flow in each direction is controlled by output-enable
(OEAB and OEBA), latch-enable (LEAB and LEBA), and
clock (CLKAB and CLKBA) inputs. The clock can be con-
trolled by the clock-enable (CLKENAB and CLKENBA)
inputs. For A-to-B data flow, the device operates in the
transparent mode when LEAB is HIGH. When LEAB is
LOW, the A data is latched if CLKAB is held at a HIGH-to-
LOW logic level. If LEAB is LOW, the A bus data is stored
in the latch/flip-flop on the LOW-to-HIGH transition of
CLKAB. When OEAB is LOW, the outputs are active. When
OEAB is HIGH, the outputs are in the high-impedance
state.
Data flow for B to A is similar to that of A to B but uses
OEBA, LEBA, CLKBA and CLKENBA.
The ALVC16601 is designed for low voltage (1.65V to
3.6V) VCC applications with I/O capability up to 3.6V.
The ALVC16601 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
s 1.65V–3.6V VCC supply operation
s 3.6V tolerant inputs and outputs
s tPD (A to B, B to A)
3.4 ns max for 3.0V to 3.6V VCC
4.0 ns max for 2.3V to 2.7V VCC
7.0 ns max for 1.65V 1.95V VCC
s Power-down high impedance inputs and outputs
s Supports live insertion/withdrawal (Note 1)
s Uses patented noise/EMI reduction circuitry
s Latchup conforms to JEDEC JED78
s ESD performance:
Human body model > 2000V
Machine model >200V
s Also packaged in plastic Fine-Pitch Ball Grid Array
(FBGA) (Preliminary)
Note 1: To ensure the high-impedance state during power up or power
down, OE should be tied to VCC through a pull-up resistor; the minimum
value of the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Order Number Package Number
Package Description
74ALVC16601GX
(Note 2)
BGA54A
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
(Preliminary) [TAPE and REEL]
74ALVC16601MTD
(Note 3)
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Note 2: BGA package available in Tape and Reel only.
Note 3: Devices also available in Tape and Reel. Specify by appending the suffix letter Xto the ordering code.
© 2001 Fairchild Semiconductor Corporation DS500682
www.fairchildsemi.com




74ALVC16601 pdf, 반도체, 판매, 대치품
Absolute Maximum Ratings(Note 7)
Supply Voltage (VCC)
DC Input Voltage (VI)
Output Voltage (VO) (Note 8)
DC Input Diode Current (IIK)
VI < 0V
DC Output Diode Current (IOK)
VO < 0V
DC Output Source/Sink Current
(IOH/IOL)
DC VCC or GND Current per
Supply Pin (ICC or GND)
Storage Temperature Range (TSTG)
0.5V to +4.6V
0.5V to 4.6V
0.5V to VCC +0.5V
50 mA
50 mA
±50 mA
±100 mA
65°C to +150°C
Recommended Operating
Conditions (Note 9)
Power Supply
Operating
1.65V to 3.6V
Input Voltage (VI)
Output Voltage (VO)
Free Air Operating Temperature (TA)
Minimum Input Edge Rate (t/V)
0V to VCC
0V to VCC
40°C to +85°C
VIN = 0.8V to 2.0V, VCC = 3.0V
10 ns/V
Note 7: The Absolute Maximum Ratings are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the Absolute Maximum Rat-
ings. The Recommended Operating Conditionstable will define the condi-
tions for actual device operation.
Note 8: IO Absolute Maximum Rating must be observed.
Note 9: Floating or unused inputs must be held HIGH or LOW.
DC Electrical Characteristics
Symbol
Parameter
VIH HIGH Level Input Voltage
VIL LOW Level Input Voltage
VOH HIGH Level Output Voltage
VOL LOW Level Output Voltage
II
IOZ
ICC
ICC
Input Leakage Current
3-STATE Output Leakage
Quiescent Supply Current
Increase in ICC per Input
Conditions
IOH = −100 µA
IOH = −4 mA
IOH = −6 mA
IOH = −12 mA
IOH = −24 mA
IOL = 100 µA
IOL = 4 mA
IOL = 6 mA
IOL = 12mA
IOL = 24 mA
0 VI 3.6V
0 VO 3.6V
VI = VCC or GND, IO = 0
VIH = VCC 0.6V
VCC
(V)
1.65 -1.95
2.3 - 2.7
2.7 - 3.6
1.65 -1.95
2.3 - 2.7
2.7 - 3.6
1.65 - 3.6
1.65
2.3
2.3
2.7
3.0
3.0
1.65 - 3.6
1.65
2.3
2.3
2.7
3
3.6
3.6
3.6
3 -3.6
Min
0.65 x VCC
1.7
2.0
VCC - 0.2
1.2
2
1.7
2.2
2.4
2
Max
0.35 x VCC
0.7
0.8
0.2
0.45
0.4
0.7
0.4
0.55
±5.0
±10
40
750
Units
V
V
V
V
µA
µA
µA
µA
www.fairchildsemi.com
4

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74ALVC16601 전자부품, 판매, 대치품
Physical Dimensions inches (millimeters) unless otherwise noted
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
Package Number BGA54A
(Preliminary)
7 www.fairchildsemi.com

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