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74ALVC16836ADGG 데이터시트 PDF




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부품번호 74ALVC16836ADGG 기능
기능 20-bit registered driver with inverted register enable 3-State
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74ALVC16836ADGG 데이터시트, 핀배열, 회로
INTEGRATED CIRCUITS
74ALVC16836A
20-bit registered driver with
inverted register enable (3-State)
Product specification
Replaces datasheet 74ALVC16836 of 2000 Jan 04
IC24 Data Handbook
2000 Mar 14
Philips
Semiconductors




74ALVC16836ADGG pdf, 반도체, 판매, 대치품
Philips Semiconductors
20-bit registered driver with inverted register enable
(3-State)
Product specification
74ALVC16836A
LOGIC SYMBOL (IEEE/IEC)
OE 27
CP 30
LE 28
Y1 3
Y2 5
Y3 6
Y4 8
Y5 9
Y6 10
Y7 12
Y8 13
Y9 14
Y10 15
Y11 16
Y12 17
Y13 19
Y14 20
Y15 21
Y16 23
Y17 24
Y18 26
EN1
2C3
C3
G2
1 1 3D
54 A1
52 A2
51 A3
49 A4
48 A5
47 A6
45 A7
44 A8
43 A9
42 A10
41 A11
40 A12
38 A13
37 A14
36 A15
34 A16
33 A17
31 A18
SH00196
FUNCTION TABLE
INPUTS
OE LE CP
OUTPUTS
A
HXXX
Z
LLXL
L
L LXH
H
LHL
L
LH
L HH
LHL
H = HIGH voltage level
L = LOW voltage level
X = Don’t care
Z = High impedance “off” state
= LOW-to-HIGH level transition
H
X
X
H
Y01
Y02
NOTES:
1. Output level before the indicated steady-state input conditions
were established, provided that CP is high before LE goes low.
2. Output level before the indicated steady-state input conditions
were established.
2000 Mar 14
4

4페이지










74ALVC16836ADGG 전자부품, 판매, 대치품
Philips Semiconductors
20-bit registered driver with inverted register enable
(3-State)
Product specification
74ALVC16836A
AC CHARACTERISTICS FOR VCC = 2.3 V TO 2.7 V RANGE
GND = 0 V; tr = tf 2.0 ns; CL = 30 pF
SYMBOL
PARAMETER
WAVEFORM
Propagation delay
An to Yn
tPHL/tPLH
Propagation delay
LE to Yn
Propagation delay
CP to Yn
tPZH/tPZL
3-State output enable time
OE to Yn
tPHZ/tPLZ
3-State output disable time
OE to Yn
CP pulse width HIGH or LOW
tW LE pulse width HIGH
Set-up time An to CP
tSU Set-up time An to LE
Hold time An to CP
th Hold time An to LE
fmax Maximum clock pulse frequency
NOTE:
1. All typical values are at VCC = 3.3 V and Tamb = 25°C.
1, 7
2, 7
4, 7
6, 7
6, 7
4, 7
2, 7
5, 7
3, 7
5, 7
3, 7
4, 7
LIMITS
VCC = 2.3 to 2.7 V
MIN
TYP1
MAX
1.0 2.4 4.2
1.3 2.8 4.5
1.4 2.8 5.0
1.4 2.2 4.0
1.4 2.0 4.5
2.0 –
2.0 –
1.0 –
1.5 –
0.6 0.2
1.4 0.4
150 300
AC CHARACTERISTICS FOR VCC = 3.0V TO 3.6V RANGE AND VCC = 2.7V
GND = 0 V; tr = tf 2.5 ns; CL = 50 pF
LIMITS
SYMBOL
PARAMETER
WAVEFORM
VCC = 3.3 ± 0.3 V
MIN TYP1, 2 MAX
Propagation delay
An to Yn
1, 7 1.0 2.3 3.6
tPHL/tPLH
Propagation delay
LE to Yn
2, 7 1.3 2.6 4.2
Propagation delay
CP to Yn
4, 7 1.3 2.5 4.2
tPZH/tPZL
3-State output enable time
OE to Yn
6, 7 1.1 2.3 4.4
tPHZ/tPLZ
3-State output disable time
OE to Yn
6, 7 1.3 2.8 4.3
CP pulse width HIGH or LOW
tW LE pulse width HIGH
4, 7
2.0 –
2, 7
2.0 –
Set-up time An to CP
tSU Set-up time An to LE
5, 7
1.0 –
3, 7
1.5 –
Hold time An to CP
th Hold time An to LE
5, 7
0.9 0.3
3, 7
1.4 0.3
fmax Maximum clock pulse frequency
NOTES:
1. All typical values are measured Tamb = 25°C.
2. Typical value is measured at VCC = 3.3 V
4, 7
150 300
LIMITS
VCC = 2.7 V
MIN TYP1 MAX
1.3 2.7 4.0
1.3 2.8 4.5
1.3 2.7 4.5
1.4 3.0 4.5
1.4 3.1 4.3
2.0 –
2.0 –
1.0 –
1.5 –
0.6 0.3
1.7 0.4
200 350
UNIT
ns
ns
ns
ns
ns
ns
MHz
UNIT
ns
ns
ns
ns
ns
ns
MHz
2000 Mar 14
7

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74ALVC16836ADGG

20-bit registered driver with inverted register enable 3-State

NXP Semiconductors
NXP Semiconductors

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