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74ALVCH162244T 데이터시트 PDF




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부품번호 74ALVCH162244T 기능
기능 Low Voltage 16-Bit Buffer/Line Driver with Bushold and 26 Series Resistor in Outputs
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74ALVCH162244T 데이터시트, 핀배열, 회로
September 2001
Revised February 2002
74ALVCH162244
Low Voltage 16-Bit Buffer/Line Driver with Bushold
and 26Series Resistor in Outputs
General Description
The ALVCH162244 contains sixteen non-inverting buffers
with 3-STATE outputs to be employed as a memory and
address driver, clock driver, or bus oriented transmitter/
receiver. The device is nibble (4-bit) controlled. Each nibble
has separate 3-STATE control inputs which can be shorted
together for full 16-bit operation.
The ALVCH162244 data inputs include active bushold cir-
cuitry, eliminating the need for external pull-up resistors to
hold unused or floating data inputs at a valid logic level
The 74ALVCH162244 is also designed with 26series
resistors in the outputs. This design reduces line noise in
applications such as memory address drivers, clock driv-
ers, and bus transceivers/transmitters.
The 74ALVCH162244 is designed for low voltage (1.65V to
3.6V) VCC applications with output capability up to 3.6V.
The 74ALVCH162244 is fabricated with an advanced
CMOS technology to achieve high speed operation while
maintaining low CMOS power dissipation.
Features
s 1.65V to 3.6V VCC supply operation
s 3.6V tolerant control inputs and outputs
s Bushold on data inputs eliminates the need for external
pull-up/pull-down resistors
s 26series resistors in outputs
s tPD
4.2 ns max for 3.0V to 3.6V VCC
4.9 ns max for 2.3V to 2.7V VCC
7.6 ns max for 1.65V to 1.95V VCC
s Uses patented noise/EMI reduction circuitry
s Latch-up conforms to JEDEC JED78
s ESD performance:
Human body model > 2000V
Machine model > 200V
Ordering Code:
Order Number
Package
Number
Package Description
74ALVCH162244T
MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Pin Names
OEn
I0I15
O0O15
Description
Output Enable Input (Active LOW)
Bushold Inputs
Outputs
© 2002 Fairchild Semiconductor Corporation DS500632
www.fairchildsemi.com




74ALVCH162244T pdf, 반도체, 판매, 대치품
AC Electrical Characteristics
Symbol
Parameter
tPHL, tPLH
tPZL, tPZH
tPLZ, tPHZ
Propagation Delay
Output Enable Time
Output Disable Time
Capacitance
TA = −40°C to +85°C, RL = 500
CL = 50 pF
CL = 30 pF
VCC = 3.3V ± 0.3V
VCC = 2.7V
VCC = 2.5V ± 0.2V VCC = 1.8V ± 0.15V
Min Max Min Max Min Max Min Max
1.0 4.2
4.7 1.0 4.9 1.5 7.6
1.0 5.6
6.7 1.0 6.8 1.5 9.8
1.0 5.5
5.7 1.0 6.3 1.5 7.2
Symbol
Parameter
Conditions
CIN
COUT
CPD
Input Capacitance
Output Capacitance
Power Dissipation Capacitance
Control
Data
Outputs Enabled
VI = 0V or VCC
VI = 0V or VCC
VI = 0V or VCC
f = 10 MHz, CL = 50 pF
Outputs Disabled f = 10 MHz, CL = 50 pF
TA = +25°C
VCC Typical
3.3 3
3.3 6
3.3 7
3.3 19
2.5 16
3.3 5
2.5 4
Units
ns
ns
ns
Units
pF
pF
pF
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