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74ALVCH162373T 데이터시트 PDF




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부품번호 74ALVCH162373T 기능
기능 Low Voltage 16-Bit Transparent Latch with Bushold and 26 Series Resistors in Outputs
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74ALVCH162373T 데이터시트, 핀배열, 회로
November 2001
Revised November 2001
74ALVCH162373
Low Voltage 16-Bit Transparent Latch with Bushold
and 26Series Resistors in Outputs
General Description
The ALVCH162373 contains sixteen non-inverting latches
with 3-STATE outputs and is intended for bus oriented
applications. The device is byte controlled. The flip-flops
appear to be transparent to the data when the Latch enable
(LE) is HIGH. When LE is LOW, the data that meets the
setup time is latched. Data appears on the bus when the
Output Enable (OE) is LOW. When OE is HIGH, the out-
puts are in a high impedance state.
The ALVCH162373 data inputs include active bushold cir-
cuitry, eliminating the need for external pull-up resistors to
hold unused or floating data inputs at a valid logic level.
The ALVCH162373 is also designed with 26series resis-
tors in the outputs. This design reduces line noise in appli-
cations such as memory address driver, clock drivers and
bus transceivers/transmitters.
The 74ALVCH162373 is designed for low voltage (1.65V to
3.6V) VCC applications with output compatibility up to 3.6V.
The 74ALVCH162373 is fabricated with an advanced
CMOS technology to achieve high speed operation while
maintaining low CMOS power dissipation.
Features
s 1.65V to 3.6V VCC supply operation
s 3.6V tolerant control inputs and outputs
s Bushold on data inputs eliminates the need for external
pull-up/pull-down resistors
s 26series resistors in outputs
s tPD (In to On)
3.8 ns max for 3.0V to 3.6V VCC
5.0 ns max for 2.3V to 2.7V VCC
9.0 ns max for 1.65V to 1.95V VCC
s Uses patented noise/EMI reduction circuitry
s Latchup conforms to JEDEC JED78
s ESD performance:
Human body model > 2000V
Machine model > 200V
Ordering Code:
Ordering Number Package Number
Package Description
74ALVCH162373T
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Pin Names
OEn
LEn
I0I15
O0O15
Description
Output Enable Input (Active LOW)
Latch Enable Input
Bushold Inputs
Outputs
© 2001 Fairchild Semiconductor Corporation DS500708
www.fairchildsemi.com




74ALVCH162373T pdf, 반도체, 판매, 대치품
AC Electrical Characteristics
Symbol
Parameter
tPHL, tPLH
tPHL, tPLH
tPZL, tPZH
tPLZ, tPHZ
tW
tS
tH
Propagation Delay
Bus to Bus
Propagation Delay
LE to Bus
Output Enable Time
Output Disable Time
Pulse Width
Setup Time
Hold Time
Capacitance
TA = −40°C to +85°C, RL = 500
CL = 50 pF
CL = 30 pF
VCC = 3.3V ± 0.3V
VCC = 2.7V
VCC = 2.5V ± 0.2V VCC = 1.8V ± 0.15V
Min Max Min Max Min Max Min Max
Units
1.3 3.8 1.5 5.0 1.0 4.5 1.5 9.0 ns
1.3 4.1 1.5 5.4 1.0 4.9 1.5 9.8 ns
1.3 4.4 1.5 5.9 1.0 5.4 1.5 9.8 ns
1.3 4.5 1.5 4.9 1.0 4.4 1.5 7.9 ns
1.5 1.5 1.5 4.0 ns
1.5 1.5 1.5 2.5 ns
1.0 1.0 1.0 1.0 ns
Symbol
Parameter
CIN
COUT
CPD
Input Capacitance
Output Capacitance
Power Dissipation Capacitance
Conditions
Outputs Enabled
VI = 0V or VCC
VI = 0V or VCC
f = 10 MHz, CL = 50 pF
TA = +25°C
VCC Typical
3.3 6
3.3 7
3.3 20
2.5 20
Units
pF
pF
pF
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관련 데이터시트

부품번호상세설명 및 기능제조사
74ALVCH162373

Low Voltage 16-Bit Transparent Latch with Bushold and 26 Series Resistors in Outputs

Fairchild Semiconductor
Fairchild Semiconductor
74ALVCH162373T

Low Voltage 16-Bit Transparent Latch with Bushold and 26 Series Resistors in Outputs

Fairchild Semiconductor
Fairchild Semiconductor

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