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PDF 74ALVCH16373T Data sheet ( Hoja de datos )
| Número de pieza | 74ALVCH16373T | |
| Descripción | Low Voltage 16-Bit Transparent Latch with Bushold | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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October 2001
Revised February 2002
74ALVCH16373
Low Voltage 16-Bit Transparent Latch with Bushold
General Description
The ALVCH16373 contains sixteen non-inverting latches
with 3-STATE outputs and is intended for bus oriented
applications. The device is byte controlled. The flip-flops
appear to be transparent to the data when the Latch
Enable (LE) is HIGH. When LE is LOW, the data that meets
the setup time is latched. Data appears on the bus when
the Output Enable (OE) is LOW. When OE is HIGH, the
outputs are in a high impedance state.
The ALVCH16373 data inputs include active bushold cir-
cuitry, eliminating the need for external pull-up resistors to
hold unused or floating data inputs at a valid logic level.
The 74ALVCH16373 is designed for low voltage (1.65V to
3.6V) VCC applications with output compatibility up to 3.6V.
The 74ALVCH16373 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
s 1.65V to 3.6V VCC supply operation
s 3.6V tolerant control inputs and outputs
s Bushold on data inputs eliminates the need for external
pull-up/pull-down resistors
s tPD (In to On)
3.6 ns max for 3.0V to 3.6V VCC
4.5 ns max for 2.3V to 2.7V VCC
6.8 ns max for 1.65V to 1.95V VCC
s Uses patented noise/EMI reduction circuitry
s Latch-up conforms to JEDEC JED78
s ESD performance:
Human body model > 2000V
Machine model > 200V
Ordering Code:
Order Number
Package
Number
Package Description
74ALVCH16373T
MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
© 2002 Fairchild Semiconductor Corporation DS500631
www.fairchildsemi.com
1 page  
AC Electrical Characteristics
Symbol
Parameter
tW
tS
tH
tPHL, tPLH
tPHL, tPLH
tPZL, tPZH
tPLZ, tPHZ
Pulse Width
Setup Time
Hold Time
Propagation Delay In to On
Propagation Delay LE to On
Output Enable Time
Output Disable Time
T A = −40°C to +85°C, RL = 500Ω
CL = 50 pF
CL = 30 pF
V CC = 3.3V ± 0.3V
V CC = 2.7V
V CC = 2.5V ± 0.2V V CC = 1.8V ± 0.15V
Min Max Min Max Min Max Min Max
3.3 3.3 3.3 4.0
1.1 1
1 2.5
1.4 1.7 1.5 1.0
1.1 3.6
4.3 1 4.5 1.5 6.8
1 3.9
4.6 1 4.9 1.5 7.8
1.0 4.7
5.7 1.0 6.0 1.5 9.2
1.4 4.1
4.5 1.2 5.1 1.5 6.8
Units
ns
ns
ns
ns
ns
ns
ns
Capacitance
Symbol
Parameter
Conditions
CIN
COUT
CPD
Input Capacitance
Output Capacitance
Power Dissipation Capacitance
Control
Data
Outputs Enabled
VI = 0V or VCC
VI = 0V or VCC
VI = 0V or VCC
f = 10 MHz, CL = 50 pF
Outputs Disabled f = 10 MHz, CL = 50 pF
TA = +25°C
VCC Typical
3.3 3
3.3 6
3.3 7
3.3 22
2.5 19
3.3 5
2.5 4
Units
pF
pF
pF
5 www.fairchildsemi.com
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet 74ALVCH16373T.PDF ] | |
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