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PDF 74ALVCH16501 Data sheet ( Hoja de datos )
| Número de pieza | 74ALVCH16501 | |
| Descripción | 18-bit universal bus transceiver | |
| Fabricantes | NXP Semiconductors | |
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74ALVCH16501
18-bit universal bus transceiver; 3-state
Rev. 5 — 10 July 2012
Product data sheet
1. General description
The 74ALVCH16501 is an 18-bit transceiver featuring non-inverting 3-state bus
compatible outputs in both send and receive directions. Data flow in each direction is
controlled by output enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock
(CPAB and CPBA) inputs. For A-to-B data flow, the device operates in the transparent
mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CPAB is held at a
HIGH or LOW logic level. If LEAB is LOW, the A-bus data is stored in the latch/flip-flop on
the LOW-to HIGH transition of CPAB. When OEAB is HIGH, the outputs are active. When
OEAB is LOW, the outputs are in the high-impedance state.
Data flow for B-to-A is similar to that of A-to-B but uses OEBA, LEBA and CPBA. The
output enables are complimentary (OEAB is active HIGH, and OEBA is active LOW.
To ensure the high-impedance state during power-up or power-down, OEBA should be
tied to VCC through a pull-up resistor and OEAB should be tied to GND through a
pull-down resistor; the minimum value of the resistor is determined by the
current-sinking/current-sourcing capability of the driver.
Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic
level.
2. Features and benefits
Wide supply voltage range from 1.2 V to 3.6 V
Complies with JEDEC standard JESD8-B
CMOS low power consumption
Direct interface with TTL levels
Current drive 24 mA at VCC = 3.0 V
Universal bus transceiver with D-type latches and D-type flip-flops capable of
operating in transparent, latched or clocked mode
All inputs have bus hold circuitry
Output drive capability 50 transmission lines at 85 C
3-state non-inverting outputs for bus-oriented applications
1 page  
NXP Semiconductors
74ALVCH16501
18-bit universal bus transceiver; 3-state
Table 2. Pin description …continued
Symbol
Pin
CPBA
30
B0 to B17
54, 52, 51, 49, 48, 47, 45, 44, 43, 42, 41, 40, 38, 37, 36, 34, 33, 31
CPAB
55
Description
clock input B-to-A
data inputs or outputs
clock input A-to-B
6. Functional description
6.1 Function table
Table 3.
Inputs
OEAB
L
H
H
H
H
H
H
H
H
Function table[1]
LEAB
X
H
H
L
L
L
L
CPAB
X
X
X
X
X
H or L
H or L
An
X
H
L
h
l
h
l
X
X
Output
Bn
Z
H
L
H
L
H
L
H
L
[1] A-to-B data flow is shown; B-to-A flow is similar but uses OEBA, LEBA and CPBA.
H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the enable or clock transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the enable or clock transition;
X = don’t care;
Z = high-impedance OFF-state;
= HIGH-to-LOW clock transition;
= LOW-to-HIGH clock transition.
7. Limiting values
Operating mode
disabled
transparent
latch data and display
clock data and display
hold data and display
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min Max
Unit
VCC supply voltage
IIK input clamping current VI < 0 V
VI input voltage
control inputs
data inputs
IOK output clamping current VO > VCC or VO < 0 V
VO output voltage
IO output current
VO = 0 V to VCC
ICC supply current
0.5
50
[1] 0.5
[1] 0.5
-
[1] 0.5
-
-
+4.6
-
+4.6
VCC + 0.5
50
VCC + 0.5
50
100
V
mA
V
V
mA
V
mA
mA
74ALVCH16501
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 10 July 2012
© NXP B.V. 2012. All rights reserved.
5 of 18
5 Page 
NXP Semiconductors
74ALVCH16501
18-bit universal bus transceiver; 3-state
LExx VI
input
CPxx
input GND
VOH
An, Bn
output
VOL
1 / fmax
VM
tW
tPHL
VM
VM
VM
tPLH
VM
001aal720
Fig 8.
Measurement points are given in Table 8.
VOL and VOH are typical output levels that occur with the output load.
Propagation delay, latch enable input (LEAB, LEBA) and clock pulse input (CPAB, CPBA) to data output,
and pulse width
VI
An, Bn
input
GND
VI
CPxx, LExx
input
GND
VM
tsu
VM
th
VM
VM
tsu
VM
th
VM
001aal722
Measurement points are given in Table 8.
Fig 9. Data set-up and hold times (An, Bn inputs to LEAB, LEBA, CPAB and CPBA inputs)
Table 8. Measurement points
Supply voltage
Input
VCC
VI
2.3 V to 2.7 V and < 2.3 V VCC
2.7 V
2.7 V
3.0 V to 3.6 V
2.7 V
VM
0.5 VCC
1.5 V
1.5 V
Output
VM
0.5 VCC
1.5 V
1.5 V
VX
VOL + 0.15 V
VOL + 0.3 V
VOL + 0.3 V
VY
VOH 0.15 V
VOH 0.3 V
VOH 0.3 V
74ALVCH16501
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 10 July 2012
© NXP B.V. 2012. All rights reserved.
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