Datasheet.kr   

74ALVT16260 데이터시트 PDF




NXP Semiconductors에서 제조한 전자 부품 74ALVT16260은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

PDF 형식의 74ALVT16260 자료 제공

부품번호 74ALVT16260 기능
기능 12-bit to 24-bit multiplexed D-type latches
제조업체 NXP Semiconductors
로고 NXP Semiconductors 로고


74ALVT16260 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.




전체 18 페이지수

미리보기를 사용할 수 없습니다

74ALVT16260 데이터시트, 핀배열, 회로
74ALVT16260
12-bit to 24-bit multiplexed D-type latches; 3-state
Rev. 03 — 20 March 2006
Product data sheet
1. General description
The 74ALVT16260 is a 12-bit to 24-bit multiplexed D-type latch used in applications where
two separate data paths must be multiplexed onto, or demultiplexed from, a single data
path. Typical applications include multiplexing or demultiplexing of address and data
information in microprocessor or bus-interface applications. This device is also useful in
memory-interleaving applications.
Three 12-bit I/O ports (A1 to A12, 1B1 to 1B12 and 2B1 to 2B12) are available for address
or data transfer. The output enable inputs (OE1B, OE2B, and OEA) control the bus
transceiver functions. OE1B and OE2B also allow bank control in the A to B direction.
Address or data information can be stored using the internal storage latches. The latch
enable inputs (LE1B, LE2B, LEA1B and LEA2B) are used to control data storage. When
the latch enable input is HIGH, the latch is transparent. When the latch enable input goes
LOW, the data present at the inputs is latched and remains latched until the latch enable
input is returned HIGH.
To ensure the high-impedance state during power-up or power-down, all output enable
inputs should be tied to VCC through a pull-up resistor. The minimum value of the resistor
is determined by the current sinking capability of the driver.
The 74ALVT16260 is available in a SSOP56 and a TSSOP56 package.
2. Features
I 5 V I/O compatible
I Bus hold inputs eliminate the need for external pull-up resistors
I Live insertion and extraction permitted
I Power-up 3-state
I Power-up reset
I Output capability: +64 mA and 32 mA
I Distributed VCC and GND pin configuration minimizes high-speed switching noise
I Latch-up protection:
N JESD78: exceeds 500 mA
I ESD protection:
N MIL STD 883C, method 3015: exceeds 2000 V
N Machine model: exceeds 200 V
芯天下--http://oneic.com/




74ALVT16260 pdf, 반도체, 판매, 대치품
Philips Semiconductors
6. Pinning information
6.1 Pinning
74ALVT16260
12-bit to 24-bit multiplexed D-type latches; 3-state
OEA 1
LE1B 2
2B3 3
GND 4
2B2 5
2B1 6
VCC 7
A1 8
A2 9
A3 10
GND 11
A4 12
A5 13
A6 14
A7 15
A8 16
A9 17
GND 18
A10 19
A11 20
A12 21
VCC 22
1B1 23
1B2 24
GND 25
1B3 26
LE2B 27
SEL 28
Fig 2. Pin configuration
74ALVT16260
56 OE2B
55 LEA2B
54 2B4
53 GND
52 2B5
51 2B6
50 VCC
49 2B7
48 2B8
47 2B9
46 GND
45 2B10
44 2B11
43 2B12
42 1B12
41 1B11
40 1B10
39 GND
38 1B9
37 1B8
36 1B7
35 VCC
34 1B6
33 1B5
32 GND
31 1B4
30 LEA1B
29 OE1B
001aae369
6.2 Pin description
Table 3.
Symbol
OEA
LE1B
2B3
GND
2B2
2B1
VCC
A1
Pin description
Pin
1
2
3
4
5
6
7
8
Description
output A enable input (active LOW)
latch 1B to A enable input
2 data input/output B3
ground (0 V)
2 data input/output B2
2 data input/output B1
supply voltage
data input/output A1
74ALVT16260_3
Product data sheet
Rev. 03 — 20 March 2006
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
4 of 18
芯天下--http://oneic.com/

4페이지










74ALVT16260 전자부품, 판매, 대치품
Philips Semiconductors
74ALVT16260
12-bit to 24-bit multiplexed D-type latches; 3-state
[1] H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
Z = high-impedance OFF-state;
1Bn = HIGH or LOW voltage level one setup time prior to the HIGH-to-LOW LEA2B transition;
2Bn = HIGH or LOW voltage level one setup time prior to the HIGH-to-LOW LEA1B transition;
active = HIGH or LOW voltage level.
8. Limiting values
Table 6. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to
GND (ground = 0 V).
Symbol Parameter
Conditions
Min Max Unit
VCC supply voltage
VI input voltage
VO output voltage
output in OFF-state or
HIGH-state
0.5
[1] 0.5
[1] 0.5
+4.6
+7.0
+7.0
V
V
V
IIK input clamping current VI < 0 V
IOK output clamping current VO < 0 V
- 50 mA
- 50 mA
IO output current
output in LOW-state
output in HIGH-state
- 128 mA
- 64 mA
Tstg storage temperature
Tj junction temperature
65
[2] -
+150 °C
150 °C
[1] The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings
are observed.
[2] The performance capability of a high-performance integrated circuit in conjunction with its thermal
environment can create junction temperatures which are detrimental to reliability.
9. Recommended operating conditions
74ALVT16260_3
Product data sheet
Table 7. Recommended operating conditions
Symbol Parameter
Conditions
VCC = 2.5 V
VCC supply voltage
VI input voltage
VIH HIGH-state input voltage
VIL LOW-state input voltage
IOH HIGH-state output current
IOL LOW-state output current
none
current duty cycle 50 %;
f 1 kHz
t/V input transition rise and fall rate outputs enabled
Tamb ambient temperature
VCC = 3.3 V
VCC supply voltage
Min Typ Max Unit
2.3 -
0-
1.7 -
--
--
--
--
--
40 -
2.7 V
5.5 V
-V
0.7 V
8 mA
8 mA
24 mA
10 ns/V
+85 °C
3.0 - 3.6 V
Rev. 03 — 20 March 2006
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
7 of 18
芯天下--http://oneic.com/

7페이지


구       성 총 18 페이지수
다운로드[ 74ALVT16260.PDF 데이터시트 ]

당사 플랫폼은 키워드, 제품 이름 또는 부품 번호를 사용하여 검색할 수 있는

포괄적인 데이터시트를 제공합니다.


구매 문의
일반 IC 문의 : 샘플 및 소량 구매
-----------------------------------------------------------------------

IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한
광범위한 전력 반도체를 판매합니다.

전력 반도체 전문업체

상호 : 아이지 인터내셔날

사이트 방문 :     [ 홈페이지 ]     [ 블로그 1 ]     [ 블로그 2 ]



관련 데이터시트

부품번호상세설명 및 기능제조사
74ALVT16260

12-bit to 24-bit multiplexed D-type latches

NXP Semiconductors
NXP Semiconductors

DataSheet.kr       |      2020   |     연락처      |     링크모음      |      검색     |      사이트맵