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74ABT16244 데이터시트 PDF




Fairchild Semiconductor에서 제조한 전자 부품 74ABT16244은 전자 산업 및 응용 분야에서
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부품번호 74ABT16244 기능
기능 16-Bit Buffer/Line Driver
제조업체 Fairchild Semiconductor
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74ABT16244 데이터시트, 핀배열, 회로
April 1992
Revised May 2005
74ABT16244
16-Bit Buffer/Line Driver with 3-STATE Outputs
General Description
The ABT16244 contains sixteen non-inverting buffers with
3-STATE outputs designed to be employed as a memory
and address driver, clock driver, or bus oriented transmit-
ter/receiver. The device is nibble controlled. Individual 3-
STATE control inputs can be shorted together for 8-bit or
16-bit operation.
Features
s Separate control logic for each nibble
s 16-bit version of the ABT244
s Outputs sink capability of 64 mA, source capability of
32 mA
s Guaranteed output skew
s Guaranteed multiple output switching specifications
s Output switching specified for both 50 pF and
250 pF loads
s Guaranteed simultaneous switching noise level and
dynamic threshold performance
s Guaranteed latchup protection
s High impedance glitch free bus loading during entire
power up and power down cycle
s Non-destructive hot insertion capability
Ordering Code:
Order Number Package Number
Package Description
74ABT16244CSSC
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
74ABT16244CMTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices are also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
Pin Descriptions
Pin Names
OEn
I0I15
O0O15
Description
Output Enable Inputs (Active LOW)
Inputs
Outputs
© 2005 Fairchild Semiconductor Corporation DS010985
www.fairchildsemi.com




74ABT16244 pdf, 반도체, 판매, 대치품
DC Electrical Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Units
VCC
CL 50 pF, RL 500:
VOLP
Quiet Output Maximum Dynamic VOL
0.4 0.7 V 5.0 TA 25qC (Note 4)
VOLV
Quiet Output Minimum Dynamic VOL
1.3 1.0
V 5.0 TA 25qC (Note 4)
VOHV
Minimum HIGH Level Dynamic Output Voltage 2.7
3.0
V 5.0 TA 25qC (Note 5)
VIHD
Minimum HIGH Level Dynamic Input Voltage
2.0
1.4
V 5.0 TA 25qC (Note 6)
VILD Maximum LOW Level Dynamic Input Voltage
1.2 0.8 V 5.0 TA 25qC (Note 6)
Note 4: Max number of outputs defined as (n). n-1 data inputs are driven 0V to 3V. One output at LOW. Guaranteed, but not tested.
Note 5: Max number of outputs defined as (n). n  1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not tested.
Note 6: Max number of data inputs (n) switching. n-1 inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (VILD), 0V to threshold (VIHD).
Guaranteed, but not tested.
AC Electrical Characteristics
Symbol
Parameter
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
Propagation
Delay Data to Outputs
Output Enable
Time
Output Disable
Time
TA 25qC
VCC 5V
CL 50 pF
Min Typ
1.0 2.3
1.0 2.7
1.5 3.5
1.5 3.5
1.0 4.2
1.0 3.2
Extended AC Electrical Characteristics
Max
3.9
3.9
6.3
6.3
6.7
6.7
TA 40qC to 85qC
VCC 4.5V5.5V
CL 50 pF
Min Max
1.0 3.9
1.0 3.9
1.5 6.3
1.5 6.3
1.0 6.7
1.0 6.7
Units
ns
ns
ns
40qC to 85qC
TA 40qC to 85qC TA 40qC to 85qC
VCC 4.5V5.5V
VCC 4.5V5.5V
VCC 4.5V5.5V
Symbol
Parameter
CL 50 pF
16 Outputs Switching
CL 250 pF
1 Output Switching
CL 250 pF
16 Outputs Switching
Units
(Note 7)
(Note 8)
(Note 9)
Min Typ Max Min Max Min Max
fTOGGLE Max Toggle Frequency
100
tPLH Propagation Delay
1.5
5.0 1.5 6.0 2.5 8.0
tPHL Data to Outputs
1.5
5.3 1.5 6.0 2.5 8.0
tPZH Output Enable Time
1.5
6.5 2.5 7.8 2.5 9.5
tPZL 1.5 6.5 2.5 7.8 2.5 8.5
tPHZ Output Disable Time
tPLZ
1.0
1.0
6.7
(Note 10)
6.7
(Note 10)
Note 7: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.).
MHz
ns
ns
ns
Note 8: This specification is guaranteed but not tested. The limits represent propagation delay with 250 pF load capacitors in place of the 50 pF load
capacitors in the standard AC load. This specification pertains to single output switching only.
Note 9: This specification is guaranteed but not tested. The limits represent propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.) with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load.
Note 10: The 3-STATE delay times are dominated by the RC network (500:, 250 pF) on the output and have been excluded from the datasheet.
www.fairchildsemi.com
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74ABT16244 전자부품, 판매, 대치품
Physical Dimensions inches (millimeters) unless otherwise noted
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
Package Number MS48A
7 www.fairchildsemi.com

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