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PDF 74ABT16899 Data sheet ( Hoja de datos )
| Número de pieza | 74ABT16899 | |
| Descripción | 18-bit latched transceiver with 16-bit parity generator/checker 3-State | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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INTEGRATED CIRCUITS
74ABT16899
74ABTH16899
18-bit latched transceiver with 16-bit
parity generator/checker (3-State)
Product specification
Supersedes data of 1997 Mar 28
IC23 Data Handbook
1998 Feb 25
Philips
Semiconductors
1 page  
Philips Semiconductors
18-bit latched transceiver with 16-bit
parity generator/checker (3-State)
Product specification
74ABT16899
74ABTH16899
BLOCK DIAGRAM
9–bit
Transparent
Latch
OE
9–bit
Output
Buffer
OEB
LEA
A0
A1
A2
A3
A4
A5
A6
A7
APAR
OEA
SEL
LE
Parity
Generator
1
mux
0
9–bit
Output
Buffer
OE
1
mux Parity
0 Generator
9–bit
Transparent
Latch
LE
ODD/
EVEN
(1 of 2 parity blocks)
FUNCTION TABLE
INPUTS
OEB OEA SEL LEA
HHXX
HL L L
HL LH
HL LX
HLHX
H L HH
LHLH
LHLH
LHL L
L HHH
L HHH
L LXX
H = High voltage level
L = Low voltage level
X = Don’t care
LEB
X
H
H
L
H
H
X
H
X
L
H
X
OPERATING MODE
3-State A bus and B bus (input A & B simultaneously)
B → A, transparent B latch, generate parity from B0 - B7, check B bus parity
B → A, transparent A & B latch, generate parity from B0 - B7, check A & B bus parity
B → A, B bus latched, generate parity from latched B0 - B7 data, check B bus parity
B → A, transparent B latch, parity feed-through, check B bus parity
B → A, transparent A & B latch, parity feed-through, check A & B bus parity
A → B, transparent A latch, generate parity from A0 - A7, check A bus parity
A → B, transparent A & B latch, generate parity from A0 - A7, check A & B bus parity
A → B, A bus latched, generate parity from latched A0 - A7 data, check A bus parity
A → B, transparent A latch, parity feed-through, check A bus parity
A → B, transparent A & B latch, parity feed-through, check A & B bus parity
Output to A bus and B bus (NOT ALLOWED)
1998 Feb 25
5
B0
B1
B2
B3
B4
B5
B6
B7
BPAR
LEB
ERRA
ERRB
SH00084
5 Page 
Philips Semiconductors
18-bit latched transceiver with 16-bit
parity generator/checker (3-State)
Product specification
74ABT16899
74ABTH16899
ODD/EVEN
0
An
(Bn)
EVEN PARITY
INPUT
APAR
(BPAR)
ERRA
(ERRB)
VM VM
tPLH
tPHL
VM VM
INPUT
OUTPUT
NOTE: Only even parity mode is shown with even parity. Odd parity mode would cause inverted output
and odd parity mode would be with ODD/EVEN = 1
SA00298
Waveform 6. Propagation Delay, APAR to ERRA or BPAR to ERRB
1
ODD/EVEN
APAR
(BPAR)
0
An
(Bn) EVEN PARITY
ODD PARITY
EVEN PARITY
INPUT
LEA
(LEB)
ERRA
(ERRB)
VM
tPLH
VM
VM
tPHL
VM
INPUT
OUTPUT
NOTE: Only odd parity mode is shown. Even parity mode would be with ODD/EVEN = o
Waveform 7. Propagation Delay, LEA to ERRA or LEB to ERRB
SA00299
1998 Feb 25
11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet 74ABT16899.PDF ] | |
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