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PDF 74ABT2541 Data sheet ( Hoja de datos )

Número de pieza 74ABT2541
Descripción Octal Buffer/Line Driver with 25 Series Resistors in the Outputs
Fabricantes Fairchild Semiconductor 
Logotipo Fairchild Semiconductor Logotipo



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No Preview Available ! 74ABT2541 Hoja de datos, Descripción, Manual

September 1992
Revised November 1999
74ABT2541
Octal Buffer/Line Driver with
25Series Resistors in the Outputs
General Description
The ABT2541 is an octal buffer and line driver designed to
drive the capacitive inputs of MOS memory drivers,
address drivers, clock drivers, and bus-oriented transmit-
ters/receivers. Functionally identical to the ABT541.
The 25series resistors in the outputs reduce ringing and
eliminate the need for external resistors.
Features
s Guaranteed output skew
s Guaranteed multiple output switching specifications
s Output switching specified for both 50 pF and
250 pF loads
s Guaranteed simultaneously switching noise level and
dynamic threshold performance
s Guaranteed latchup protection
s High impedance glitch free bus loading during entire
power up and power down cycle
s Nondestructive hot insertion capability
s Disable time less than enable time to avoid bus
contention
Ordering Code:
Order Number Package Number
Package Description
74ABT2541CSC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300Wide Body
74ABT2541CSJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ABT2541CMSA
MSA20
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
74ABT2541CMTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names
OE1, OE2
I0I7
O0O7
Description
Output Enable Input (Active LOW)
Inputs
Outputs
Schematic of Each Output
Truth Table
Inputs
OE1
L
OE2
L
HX
XH
LL
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
© 1999 Fairchild Semiconductor Corporation DS011502
Outputs
I
HH
XZ
XZ
LL
www.fairchildsemi.com

1 page




74ABT2541 pdf
AC Loading
*Includes jig and probe capacitance.
FIGURE 1. Standard AC Test Load
FIGURE 2. Test Input Signal Levels
AC Waveforms
Amplitude Rep. Rate
tW
tr
3.0V
1 MHz
500 ns
2.5 ns
FIGURE 3. Test Input Signal Requirements
tf
2.5 ns
FIGURE 4. Propagation Delay Waveforms for
Inverting and Non-Inverting Functions
FIGURE 6. 3-STATE Output HIGH and
LOW Enable and Disable Times
FIGURE 5. Propagation Delay, Pulse Width Waveforms
FIGURE 7. Setup Time, Hold Time
and Recovery Time Waveforms
5 www.fairchildsemi.com

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