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74ABT273CMTC 데이터시트 PDF




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부품번호 74ABT273CMTC 기능
기능 Octal D-Type Flip-Flop
제조업체 Fairchild Semiconductor
로고 Fairchild Semiconductor 로고


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74ABT273CMTC 데이터시트, 핀배열, 회로
January 1993
Revised November 1999
74ABT273
Octal D-Type Flip-Flop
General Description
The ABT273 has eight edge-triggered D-type flip-flops with
individual D inputs and Q outputs. The common buffered
Clock (CP) and Master Reset (MR) inputs load and reset
(clear) all flip-flops simultaneously.
The register is fully edge-triggered. The state of each D
input, one setup time before the LOW-to-HIGH clock transi-
tion, is transferred to the corresponding flip-flop’s Q output.
All outputs will be forced LOW independently of Clock or
Data inputs by a LOW voltage level on the MR input. The
device is useful for applications where the true output only
is required and the Clock and Master Reset are common to
all storage elements.
Features
s Eight edge-triggered D-type flip-flops
s Buffered common clock
s Buffered, asynchronous Master Reset
s See ABT377 for clock enable version
s See ABT373 for transparent latch version
s See ABT374 for 3-STATE version
s Output sink capability of 64 mA, source capability of
32 mA
s Guaranteed latchup protection
s High impedance glitch free bus loading during entire
power up and power down cycle
s Non-destructive hot insertion capability
s Disable time less than enable time to avoid bus conten-
tion
Ordering Code:
Order Number Package Number
Package Description
74ABT273CSC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300Wide Body
74ABT273CSJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ABT273CMSA
MSA20
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
74ABT273CMTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter Xto the ordering code.
Connection Diagram
Pin Descriptions
Pin Names
D0D7
MR
CP
Q0Q7
Description
Data Inputs
Master Reset (Active LOW)
Clock Pulse Input (Active Rising Edge)
Data Outputs
© 1999 Fairchild Semiconductor Corporation DS011549
www.fairchildsemi.com




74ABT273CMTC pdf, 반도체, 판매, 대치품
AC Electrical Characteristics
(SSOIC package)
Symbol
Parameter
fMAX
tPLH
tPHL
tPHL
Maximum Clock Frequency
Propagation Delay
CP to On
Propagation Delay
MR to On
TA = +25°C
VCC = +5.0V
CL = 50 pF
Min Typ
150 200
2.0
2.8
2.5
AC Operating Requirements
Max
6.0
6.8
7.4
TA = −55°C to +125°C
VCC = 4.5V to 5.5V
CL = 50 pF
Min Max
150
1.0 7.0
1.0 7.5
TA = −40°C to +85°C
VCC = 4.5V to 5.5V
CL = 50 pF
Min Max
150
2.0 6.0
2.8 6.8
1.0 8.2 2.5 7.4
Units
MHz
ns
ns
Symbol
Parameter
tS(H)
tS(L)
tH(H)
tH(L)
tW(H)
tW(L)
tW(L)
tREC
Setup Time, HIGH
or LOW Dn to CP
Hold Time, HIGH
or LOW Dn to CP
Pulse Width, CP,
HIGH or LOW
Master Reset Pulse
Width, LOW
Recovery Time
MR to CP
TA = +25°C
VCC = +5.0V
CL = 50 pF
Min Max
2.0
2.5
1.2
1.2
3.3
3.3
3.3
TA = −55°C to +125°C
VCC = 4.5V to 5.5V
CL = 50 pF
Min Max
2.0
2.5
1.4
1.4
3.3
3.3
TA = −40°C to +85°C
VCC = 4.5V to 5.5V
CL = 50 pF
Min Max
2.0
2.5
1.2
1.2
3.3
3.3
3.3 3.3
2.0 2.0 2.0
Units
ns
ns
ns
ns
ns
Capacitance
(SOIC package)
Symbol
Parameter
Typ
CIN
COUT (Note 5)
Input Capacitance
Output Capacitance
5
9
Note 5: COUT is measured at frequency f = 1 MHz, per MIL-STD-833, Method 3012.
Units
pF
pF
VCC = 0V
VCC = 5.0V
Conditions
TA = 25°C
www.fairchildsemi.com
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74ABT273CMTC 전자부품, 판매, 대치품
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
7 www.fairchildsemi.com

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부품번호상세설명 및 기능제조사
74ABT273CMTC

Octal D-Type Flip-Flop

Fairchild Semiconductor
Fairchild Semiconductor

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