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74ABT821PW 데이터시트 PDF




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부품번호 74ABT821PW 기능
기능 10-bit D-type flip-flop; positive-edge trigger 3-State
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74ABT821PW 데이터시트, 핀배열, 회로
Philips Semiconductors
10-bit D-type flip-flop; positive-edge trigger
(3-State)
Product specification
74ABT821
FEATURES
High speed parallel registers with positive edge-triggered D-type
flip-flops
Ideal where high speed, light loading, or increased fan-in are
required with MOS microprocessors
Output capability: +64mA/–32mA
Latch-up protection exceeds 500mA per Jedec Std 17
ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model
Power-up 3-State
Power-up Reset
DESCRIPTION
The 74ABT821 high-performance BiCMOS device combines low
static and dynamic power dissipation with high speed and high
output drive.
The 74ABT821 Bus interface Register is designed to eliminate the
extra packages required to buffer existing registers and provide
extra data width for wider data/address paths of buses carrying
parity.
The 74ABT821 is a buffered 10-bit wide version of the
74ABT374/74ABT534 functions.
The 74ABT821 is a 10-bit, edge triggered register coupled to ten
3-State output buffers. The two sections of the device are controlled
independently by the clock (CP) and Output Enable (OE) control
gates.
The register is fully edge triggered. The state of each D input, one
set-up time before the Low-to-High clock transition is transferred to
the corresponding flip-flop’s Q output.
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors.
The active Low Output Enable (OE) controls all ten 3-State buffers
independent of the register operation. When OE is Low, the data in
the register appears at the outputs. When OE is High, the outputs
are in high impedance ”off” state, which means they will neither drive
nor load the bus.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
tPLH
tPHL
CIN
COUT
ICCZ
Propagation delay
CP to Qn
Input capacitance
Output capacitance
Total supply current
CONDITIONS
Tamb = 25°C; GND = 0V
CL = 50pF; VCC = 5V
VI = 0V or VCC
Outputs disabled; VO = 0V or VCC
Outputs disabled; VCC =5.5V
TYPICAL
4.6
4
7
500
UNIT
ns
pF
pF
nA
ORDERING INFORMATION
PACKAGES
24-Pin Plastic DIP
24-Pin plastic SO
24-Pin Plastic SSOP Type II
24-Pin Plastic TSSOP Type I
TEMPERATURE RANGE
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
OUTSIDE NORTH AMERICA
74ABT821 N
74ABT821 D
74ABT821 DB
74ABT821 PW
NORTH AMERICA
74ABT821 N
74ABT821 D
74ABT821 DB
74ABT821PW DH
DWG NUMBER
SOT222-1
SOT137-1
SOT340-1
SOT355-1
PIN CONFIGURATION
OE 1
D0 2
D1 3
D2 4
D3 5
D4 6
D5 7
TOP VIEW
D6 8
D7 9
D8 10
D9 11
GND 12
24 VCC
23 Q0
22 Q1
21 Q2
20 Q3
19 Q4
18 Q5
17 Q6
16 Q7
15 Q8
14 Q9
13 CP
PIN DESCRIPTION
PIN NUMBER
SYMBOL
1 OE
2, 3, 4, 5, 6,
7, 8, 9, 10, 11
23, 22, 21, 20, 19,
18, 17, 16, 15, 14
D0-D9
Q0-Q9
13 CP
10 GND
20 VCC
FUNCTION
Output enable input
(active-Low)
Data inputs
Data outputs
Clock pulse input (active
rising edge)
Ground (0V)
Positive supply voltage
SA00223
1995 Sep 06
1 853-1616 15703




74ABT821PW pdf, 반도체, 판매, 대치품
Philips Semiconductors
10-bit D-type flip-flop; positive-edge trigger
(3-State)
Product specification
74ABT821
DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Tamb = +25°C
Tamb = –40°C
to +85°C
UNIT
Min Typ Max Min Max
VIK Input clamp voltage
VOH High-level output voltage
VOL
VRST
Low-level output voltage
Power-up output low
voltage3
VCC = 4.5V; IIK = –18mA
VCC = 4.5V; IOH = –3mA; VI = VIL or VIH
VCC = 5.0V; IOH = –3mA; VI = VIL or VIH
VCC = 4.5V; IOH = –32mA; VI = VIL or VIH
VCC = 4.5V; IOL = 64mA; VI = VIL or VIH
VCC = 5.5V; IO = 1mA; VI = GND or VCC
–0.9 –1.2
–1.2
2.5 2.9
2.5
3.0 3.4
3.0
2.0 2.4
2.0
0.42 0.55
0.55
0.13 0.55
0.55
V
V
V
V
V
V
II Input leakage current
VCC = 5.5V; VI = GND or 5.5V
±0.01 ±1.0
±1.0 µA
IOFF Power-off leakage current
VCC = 0.0V; VO or VI 4.5V
±5.0 ±100
±100 µA
IPU/IPD
Power-up/down 3-State
output current4
VCC = 2.0V; VO = 0.5V; VI = GND or VCC;
V OE = VCC
±5.0 ±50
±50 µA
IOZH 3-State output High current VCC = 5.5V; VO = 2.7V; VI = VIL or VIH
5.0 50
50 µA
IOZL 3-State output Low current VCC = 5.5V; VO = 0.5V; VI = VIL or VIH
–5.0 –50
–50 µA
ICEX
IO
Output High leakage current
Output current1
VCC = 5.5V; VO = 5.5V; VI = GND or VCC
VCC = 5.5V; VO = 2.5V
5.0 50
50 µA
–50 –100 –180 –50 –180 mA
ICCH
VCC = 5.5V; Outputs High, VI = GND or VCC
0.5 250
250 µA
ICCL Quiescent supply current
VCC = 5.5V; Outputs Low, VI = GND or VCC
25 38
38 mA
ICCZ
VCC = 5.5V; Outputs 3-State;
VI = GND or VCC
0.5 250
250 µA
ICC
Additional supply current per VCC = 5.5V; one input at 3.4V,
input pin2
other inputs at VCC or GND
0.5 1.5
1.5 mA
NOTES:
1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
2. This is the increase in supply current for each input at 3.4V.
3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.
4. This parameter is valid for any VCC between 0V and 2.1V with a transition time of up to 10msec. For VCC = 2.1V to VCC = 5V " 10%, a
transition time of up to 100µsec is permitted.
AC CHARACTERISTICS
GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω
SYMBOL
PARAMETER
WAVEFORM
fMAX
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
Maximum clock frequency
Propagation delay
CP to Qn
Output enable time
to High and Low level
Output disable time
from High and Low level
1
1
3
4
3
4
LIMITS
Tamb = +25oC
VCC = +5.0V
Min Typ Max
125 185
2.1 4.1 5.6
2.8 4.6 6.2
1.0 3.0 4.5
2.2 4.1 5.6
2.7 4.7 6.2
2.8 4.6 6.1
Tamb = -40 to
+85oC
VCC = +5.0V ±0.5V
Typ Max
125
2.1 6.2
2.8 6.7
1.0 5.3
2.2 6.3
2.7 6.7
2.8 6.5
UNIT
ns
ns
ns
ns
1995 Sep 06
4

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