Datasheet.kr   

74ABT841 데이터시트 PDF




NXP Semiconductors에서 제조한 전자 부품 74ABT841은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


PDF 형식의 74ABT841 자료 제공

부품번호 74ABT841 기능
기능 10-bit bus interface latch 3-State
제조업체 NXP Semiconductors
로고 NXP Semiconductors 로고


74ABT841 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.




전체 7 페이지수

미리보기를 사용할 수 없습니다

74ABT841 데이터시트, 핀배열, 회로
Philips Semiconductors Advanced BiCMOS Products
Octal inverting transceiver with parity
generator/checker (3–State)
Objective specification
74ABT834
FEATURES
Low static and dynamic power dissipation
with high speed and high output drive
Open–collector ERROR output
Output capability: +64mA/–32mA
Latch–up protection exceeds 500mA per
Jedec JC40.2 Std 17
ESD protection exceeds 2000 V per MIL
STD 883C Method 3015.6 and 200 V per
Machine Model
Power up/down 3–State
DESCRIPTION
The 74ABT834 high–performance BiCMOS
device combines low static and dynamic
QUICK REFERENCE DATA
SYMBOL
PARAMETER
tPLH
tPHL
tPLH
tPHL
CIN
COUT
ICCZ
Propagation delay
An to Bn or Bn to An
Propagation delay
An to PARITY
Input capacitance
Output capacitance
Total supply current
power dissipation with high speed and high
output drive.
The 74ABT834 is an octal inverting
transceiver with a parity generator/checker
and is intended for bus–oriented applications.
When Output Enable A (OEA) is High, it will
place the A outputs in a high impedance
state. Output Enable B (OEB) controls the B
outputs in the same way.
The parity generator creates an odd parity
output (PARITY) when OEB is Low. When
OEA is Low, the parity of the B port, including
the PARITY input, is checked for odd parity.
When an error is detected, the error data is
sent to the input of a storage register. If a
Low–to–High transition happens at the clock
input (CP), the error data is stored in the
register and the Open–collector error flag
(ERROR) will go Low. The error flag register
is cleared with a Low pulse on the CLEAR
input.
If both OEA and OEB are Low, data will flow
from the A bus to the B bus and the part is
forced into an error condition which creates
an inverted PARITY output. This error
condition can be used by the designer for
system diagnostics.
CONDITIONS
Tamb = 25°C; GND = 0V
CL = 50pF; VCC = 5V
CL = 50pF; VCC = 5V
VI = 0V or VCC
VI = 0V or VCC
Outputs disabled; VCC =5.5V
TYPICAL
3.4
7.4
4
7
50
UNIT
ns
ns
pF
pF
µA
ORDERING INFORMATION
PACKAGES
24–pin plastic DIP (300mil)
24–pin plastic SOL (300mil)
PIN CONFIGURATION
CONDITIONS
Tamb = 25°C; GND = 0V
–40°C to +85°C
–40°C to +85°C
LOGIC SYMBOL
ORDER CODE
74ABT834N
74ABT834D
OEA 1
A0 2
A1 3
A2 4
A3 5
A4 6
A5 7
A6 8
A7 9
ERROR 10
CLEAR 11
GND 12
24 VCC
23 B0
22 B1
21 B2
20 B3
19 B4
18 B5
17 B6
16 B7
15 PARITY
14 OEB
13 CP
TOP VIEW
June 9, 1992
23456789
A0 A1 A2 A3 A4 A5 A6 A7
14 OEB
1 OEA
PARITY
15
11 CLEAR
ERROR
10
13 CP
B0 B1 B2 B3 B4 B5 B6 B7
23 22 21 20 19 18 17 16
1




74ABT841 pdf, 반도체, 판매, 대치품
Philips Semiconductors Advanced BiCMOS Products
Octal inverting transceiver with parity
generator/checker (3–State)
Objective specification
74ABT834
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
VCC
VI
VIH
VIL
VOH
IOH
IOL
t/v
Tamb
DC supply voltage
Input voltage
High–level input voltage
Input voltage
High–level output voltage, ERROR
High–level output current
Low–level output current
Input transition rise or fall rate
Operating free–air temperature range
LIMITS
Min Max
4.5 5.5
0 VCC
2.0
0.8
5.5
–32
64
05
–40 +85
UNIT
V
V
V
V
V
mA
mA
ns/V
°C
DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Tamb = +25°C
Tamb = –40°C
to +85°C
UNIT
Min Typ Max Min Max
VIK Input clamp voltage
VCC = 4.5V; IIK = –18mA
IOH
High–level output current
ERROR ONLY
VCC = 5.5V; VOH = 5.5V; VI = VIL or VIH
–0.9 –1.2
20
–1.2 V
20 µA
VOH
VOL
II
IIH + IOZH
IIL + IOZL
IO
ICCH
ICCL
ICCZ
ICC
High–level output voltage
Low–level output voltage
Input leakage Control pins
current
Data pins
3–State output High current
3–State output Low current
Output current1
Quiescent supply current
Additional supply current per
input pin2
VCC = 4.5V; IOH = –3mA; VI = VIL or VIH
VCC = 5.0V; IOH = –3mA; VI = VIL or VIH
VCC = 4.5V; IOH = –32mA; VI = VIL or VIH
VCC = 4.5V; IOL = 64mA; VI = VIL or VIH
VCC = 5.5V; VI = GND or 5.5V
VCC = 5.5V; VI = GND or 5.5V
VCC = 5.5V; VO = 2.7V; VI = VIL or VIH
VCC = 5.5V; VO = 0.5V; VI = VIL or VIH
VCC = 5.5V; VO = 2.5V
VCC = 5.5V; Outputs High, VI = GND or VCC
VCC = 5.5V; Outputs Low, VI = GND or VCC
VCC = 5.5V; Outputs 3–State;
VI = GND or VCC
VCC = 5.5V; one input at 3.4V,
other inputs at VCC or GND
2.5 3.5
2.5
3.0 4.0
3.0
2.0 2.6
2.0
0.42 0.55
0.55
±0.01 ±1.0
±5 ±100
±1.0
±100
5.0 50
50
–5.0 –50
–50
–50 –80 –180 –50 –180
50 250
250
20 30
30
50 250
250
0.3 1.5
1.5
V
V
V
V
µA
µA
µA
µA
mA
µA
mA
µA
mA
NOTES:
1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
2. This is the increase in supply current for each input at 3.4V.
June 9, 1992
4

4페이지










74ABT841 전자부품, 판매, 대치품
Philips Semiconductors Advanced BiCMOS Products
Octal inverting transceiver with parity
generator/checker (3–State)
Objective specification
74ABT834
TYPICAL PROPAGATION DELAYS VERSUS LOAD FOR OPEN COLLECTOR OUTPUTS
18
16
14
12
tPLH
10
8
6
4
tPHL
2
0
0 100 200 300 400 500 600
Load resistor ()
NOTE:
When using Open–Collector parts, the value of the pull–up resistor greatly affects the value of the tPLH. For example, changing the
specified pull–up resistor value from 500to 100will improve the tPLH over 300% with only a slight change in the tPHL. However,
if the value of the pull–up resistor is changed, the user must make certain that the total IOL current through the resistor and the total
IIL’s of the receivers does not exceed the IOL maximum specification.
TEST CIRCUIT AND WAVEFORM
VCC
PULSE
GENERATOR
VIN
RT
D.U.T
VOUT
CL
RX
RL
Test Circuit for 3–State Outputs
SWITCH POSITION
TEST SWITCH
tPLZ
tPZL
All other
closed
closed
open
LOAD VALUES
OUTPUT RX VX
ERROR 100VCC
All other 5007.0V
90%
VX NEGATIVE
PULSE
POSITIVE
PULSE
10%
VM
10%
tW
VM
10%
tTHL (tF)
tTLH (tR)
90%
VM
90%
VM
tW
VM = 1.5V
Input Pulse Definition
90%
AMP (V)
0V
tTLH (tR)
tTHL (tF)
AMP (V)
10%
0V
DEFINITIONS
RL = Load resistor; see AC CHARACTERISTICS for value.
CL = Load capacitance includes jig and probe capacitance;
see AC CHARACTERISTICS for value.
RT = Termination resistance should be equal to ZOUT of
pulse generators.
FAMILY
74ABT
INPUT PULSE REQUIREMENTS
Amplitude Rep. Rate tW tR tF
3.0V
1MHz
500ns 2.5ns 2.5ns
June 9, 1992
7

7페이지


구       성 총 7 페이지수
다운로드[ 74ABT841.PDF 데이터시트 ]

당사 플랫폼은 키워드, 제품 이름 또는 부품 번호를 사용하여 검색할 수 있는

포괄적인 데이터시트를 제공합니다.


구매 문의
일반 IC 문의 : 샘플 및 소량 구매
-----------------------------------------------------------------------

IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한
광범위한 전력 반도체를 판매합니다.

전력 반도체 전문업체

상호 : 아이지 인터내셔날

사이트 방문 :     [ 홈페이지 ]     [ 블로그 1 ]     [ 블로그 2 ]



관련 데이터시트

부품번호상세설명 및 기능제조사
74ABT841

10-bit bus interface latch 3-State

NXP Semiconductors
NXP Semiconductors
74ABT841D

10-bit bus interface latch 3-State

NXP Semiconductors
NXP Semiconductors

DataSheet.kr       |      2020   |     연락처      |     링크모음      |      검색     |      사이트맵