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74ABT845PW 데이터시트 PDF




NXP Semiconductors에서 제조한 전자 부품 74ABT845PW은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


PDF 형식의 74ABT845PW 자료 제공

부품번호 74ABT845PW 기능
기능 8-bit bus interface latch with set and reset 3-State
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74ABT845PW 데이터시트, 핀배열, 회로
Philips Semiconductors
8-bit bus interface latch with set and reset
(3-State)
Product specification
74ABT845
FEATURES
High speed parallel latches
Ideal where high speed, light loading, or increased fan-in are
required with MOS microprocessors
Broadside pinout
Output capability: +64mA/–32mA
Power-up 3-State
Power-up reset
Latch-up protection exceeds 500mA per Jedec Std 17
ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model
DESCRIPTION
The 74ABT845 consists of eight D-type latches with 3-State outputs.
In addition to the LE, OE, MR and PRE pins, the 74ABT845 has two
additional OE pins, making a total of three Output Enable (OE0,
OE1, OE2) pins. The multiple Output enables allow multiuser control
of the interface, e.g., CS, DMA, and RD/WR.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
tPLH
tPHL
CIN
COUT
ICCZ
Propagation delay
Dn to Qn
Input capacitance
Output capacitance
Total supply current
CONDITIONS
Tamb = 25°C; GND = 0V
CL = 50pF; VCC = 5V
VI = 0V or VCC
Outputs disabled;
VO = 0V or VCC
Outputs disabled; VCC = 5.5V
TYPICAL
5.4
4
7
500
UNIT
ns
pF
pF
nA
ORDERING INFORMATION
PACKAGES
24-Pin Plastic DIP
24-Pin plastic SO
24-Pin Plastic SSOP Type II
24-Pin Plastic TSSOP Type I
TEMPERATURE RANGE OUTSIDE NORTH AMERICA
–40°C to +85°C
74ABT845 N
–40°C to +85°C
74ABT845 D
–40°C to +85°C
74ABT845 DB
–40°C to +85°C
74ABT845 PW
NORTH AMERICA
74ABT845 N
74ABT845 D
74ABT845 DB
74ABT845PW DH
DWG NUMBER
SOT222-1
SOT137-1
SOT340-1
SOT355-1
PIN CONFIGURATION
OE0 1
OE1 2
D0 3
D1 4
D2 5
D3 6
D4 7
D5 8
D6 9
D7 10
MR 11
GND 12
24 VCC
23 OE2
22 Q0
21 Q1
20 Q2
19 Q3
18 Q4
17 Q5
16 Q6
15 Q7
14 PRE
13 LE
TOP VIEW
PIN DESCRIPTION
PIN NUMBER SYMBOL
FUNCTION
1, 2, 23
OE0 – OE2
Output enable inputs
(active-Low)
3, 4, 5, 6,
7, 8, 9, 10
D0-D7 Data inputs
22, 21, 20, 19,18,
17, 16, 15
Q0-Q7
Data outputs
11 MR Master reset input (active-Low)
13
LE
Latch enable input
(active-High)
14
PRE
Preset input (active-Low)
12 GND Ground (0V)
24 VCC Positive supply voltage
SA00258
1995 Sep 06
1 853-1703 15702




74ABT845PW pdf, 반도체, 판매, 대치품
Philips Semiconductors
8-bit bus interface latch with set and reset
(3-State)
Product specification
74ABT845
DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Tamb = +25°C
Tamb = –40°C
to +85°C
UNIT
Min Typ Max Min Max
VIK Input clamp voltage
VOH High–level output voltage
VOL
VRST
Low–level output voltage
Power-up output low
voltage3
VCC = 4.5V; IIK = –18mA
VCC = 4.5V; IOH = –3mA; VI = VIL or VIH
VCC = 5.0V; IOH = –3mA; VI = VIL or VIH
VCC = 4.5V; IOH = –32mA; VI = VIL or VIH
VCC = 4.5V; IOL = 64mA; VI = VIL or VIH
VCC = 5.5V; IO = 1mA; VI = GND or VCC
–0.9 –1.2
–1.2
2.5 2.9
2.5
3.0 3.4
3.0
2.0 2.4
2.0
0.42 0.55
0.55
0.13 0.55
0.55
V
V
V
V
V
V
II Input leakage current
IOFF Power-off leakage current
VCC = 5.5V; VI = GND or 5.5V
VCC = 0.0V; VO or VI 4.5V
±0.01 ±1.0
±5.0 ±100
±1.0
±100
µA
µA
IPU/PD
Power-up/down
3-state output current4
VCC = 2.1V; VO = 0.5V; V OE = VCC;
VI = GND or VCC
±5.0 ±50
±50 µA
IOZH 3-State output High current VCC = 5.5V; VO = 2.7V; VI = VIL or VIH
5.0 50
50 µA
IOZL 3-State output Low current VCC = 5.5V; VO = 0.5V; VI = VIL or VIH
–5.0 –50
–50 µA
ICEX
IO
Output High leakage current
Output current1
VCC = 5.5V; VO = 5.5V; VI = GND or VCC
VCC = 5.5V; VO = 2.5V
5.0 50
50 µA
–50 –80 –180 –50 –180 mA
ICCH
VCC = 5.5V; Outputs High, VI = GND or VCC
0.5 250
250 µA
ICCL Quiescent supply current
VCC = 5.5V; Outputs Low, VI = GND or VCC
24 30
30 mA
ICCZ
VCC = 5.5V; Outputs 3-State;
VI = GND or VCC
0.5 250
250 µA
ICC
Additional supply current per VCC = 5.5V; one input at 3.4V,
input pin2
other inputs at VCC or GND
0.5 1.5
1.5 mA
NOTES:
1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
2. This is the increase in supply current for each input at 3.4V.
3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.
4. This parameter is valid for any VCC between 0V and 2.1V with a transition time of up to 10msec. For VCC = 2.1V to VCC = 5V " 10%, a
transition time of up to 100µsec is permitted.
1995 Sep 06
4

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74ABT845PW 전자부품, 판매, 대치품
Philips Semiconductors
8-bit bus interface latch with set and reset
(3-State)
Product specification
74ABT845
TEST CIRCUIT AND WAVEFORM
VCC
PULSE
GENERATOR
VIN
RT
D.U.T.
VOUT
CL
RL
RL
Test Circuit for 3-State Outputs
SWITCH POSITION
TEST SWITCH
tPLZ
tPZL
All other
closed
closed
open
7.0V
90%
NEGATIVE
PULSE
POSITIVE
PULSE
10%
VM
10%
tW
VM
10%
tTHL (tF)
tTLH (tR)
90%
VM
90%
VM
tW
VM = 1.5V
Input Pulse Definition
90%
AMP (V)
0V
tTLH (tR)
tTHL (tF)
AMP (V)
10%
0V
DEFINITIONS
RL = Load resistor; see AC CHARACTERISTICS for value.
CL = Load capacitance includes jig and probe capacitance;
see AC CHARACTERISTICS for value.
RT = Termination resistance should be equal to ZOUT of
pulse generators.
FAMILY
74ABT
INPUT PULSE REQUIREMENTS
Amplitude Rep. Rate tW tR tF
3.0V
1MHz 500ns 2.5ns 2.5ns
SA00012
1995 Sep 06
7

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