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부품번호 | 74ABT899 기능 |
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기능 | 9-Bit Latchable Transceiver with Parity Generator/Checker | ||
제조업체 | Fairchild Semiconductor | ||
로고 | |||
전체 16 페이지수
INTEGRATED CIRCUITS
74ABT899
9-bit dual latch transceiver with 8-bit
parity generator/checker (3-State)
Product specification
Supersedes data of 1993 Oct 04
IC23 Data Handbook
1998 Jan 16
Philips
Semiconductors
Philips Semiconductors
9-bit dual latch transceiver with 8-bit parity
generator/checker (3-State)
Product specification
74ABT899
9–bit
Transparent
Latch
OE
9–bit
Output
Buffer
27 OEB
LEA
A0
A1
A2
A3
A4
A5
A6
A7
APAR
3
4
5
6
7
8
9
10
11
12
OEA 13
SEL 16
ODD/
EVEN
1
LE
Parity
Generator
1
mux
0
9–bit
Output
Buffer
OE
1
mux Parity
0 Generator
9–bit
Transparent
Latch
LE
26 B0
25 B1
24 B2
23 B3
22 B4
21 B5
20 B6
19 B7
18 BPAR
17 LEB
2 ERRA
15 ERRB
SA00292
FUNCTION TABLE
INPUTS
OEB OEA SEL LEA
HHXX
HL L L
HL LH
HL LX
HLHX
H L HH
LHLH
LHLH
LHL L
L HHH
L HHH
L LXX
H = High voltage level
L = Low voltage level
X = Don’t care
LEB
X
H
H
L
H
H
X
H
X
L
H
X
OPERATING MODE
3-State A bus and B bus (input A & B simultaneously)
B → A, transparent B latch, generate parity from B0 - B7, check B bus parity
B → A, transparent A & B latch, generate parity from B0 - B7, check A & B bus parity
B → A, B bus latched, generate parity from latched B0 - B7 data, check B bus parity
B → A, transparent B latch, parity feed-through, check B bus parity
B → A, transparent A & B latch, parity feed-through, check A & B bus parity
A → B, transparent A latch, generate parity from A0 - A7, check A bus parity
A → B, transparent A & B latch, generate parity from A0 - A7, check A & B bus parity
A → B, A bus latched, generate parity from latched A0 - A7 data, check A bus parity
A → B, transparent A latch, parity feed-through, check A bus parity
A → B, transparent A & B latch, parity feed-through, check A & B bus parity
Output to A bus and B bus (NOT ALLOWED)
1998 Jan 16
4
4페이지 Philips Semiconductors
9-bit dual latch transceiver with 8-bit parity
generator/checker (3-State)
Product specification
74ABT899
AC CHARACTERISTICS
GND = 0V; tR = tF = 2.5ns; CL = 50pF, RL = 500Ω
SYMBOL
PARAMETER
WAVEFORM
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
Propagation delay
An to Bn or Bn to An
Propagation delay
An to BPAR or Bn to APAR
Propagation delay
An to ERRA or Bn to ERRB
Propagation delay
APAR to BPAR or BPAR to APAR
Propagation delay
APAR to ERRA or BPAR to ERRB
Propagation delay
ODD/EVEN to APAR or BPAR
Propagation delay
ODD/EVEN to ERRA or ERRB
Propagation delay
SEL to APAR or BPAR
Propagation delay
SEL to ERRA or ERRB
Propagation delay
LEA to Bn or LEB to An
Propagation delay
LEA to BPAR or LEB to APAR
Propagation delay
LEA to ERRA or LEB to ERRB
Output enable time
OEA to An, APAR or OEB to Bn, BPAR
Output disable time
OEA to An, APAR or OEB to Bn, BPAR
AC SETUP REQUIREMENTS
GND = 0V; tR = tF = 2.5ns; CL = 50pF, RL = 500Ω
1
2
3
1
6
5
4
8
8
9
9
7
11, 12
11, 12
SYMBOL
PARAMETER
WAVEFORM
ts(H)
ts(L)
th(H)
th(L)
tw(H)
Setup time, High or Low
An, APAR to LEA or Bn, BPAR to LEB
Hold time, High or Low
An, APAR to LEA or Bn, BPAR to LEB
Pulse width, High
LEA or LEB
10
10
10
LIMITS
Tamb = +25oC
VCC = +5.0V
CL = 50pF
RL = 500Ω
Min Typ Max
Tamb = –40 to +85oC
VCC = +5.0V ±10%
CL = 50pF
RL = 500Ω
Min Max
1.0 3.2 4.5 1.0 4.9
1.0 2.7 4.1 1.0 4.6
3.0 6.0 7.5 3.0 9.0
2.5 6.4 7.9 2.5 8.8
2.8 6.0 8.0 2.8 9.1
2.8 6.7 8.5 2.8 9.3
2.0 4.0 5.2 2.0 5.7
1.3 3.2 4.4 1.3 5.0
1.5 4.2 5.4 1.5 6.0
1.5 4.0 5.4 1.5 6.1
2.6 5.5 6.8 2.6 8.1
2.5 5.3 6.7 2.5 7.8
2.3 5.4 6.8 2.3 7.9
2.6 5.7 7.2 2.6 8.4
1.3 4.1 5.2 1.3 6.0
1.4 4.1 5.3 1.4 5.9
3.7 6.8 8.3 3.7 9.8
5.1 8.3 9.7 5.1 11.0
1.0 3.2 4.4 1.0 4.9
1.0 3.1 4.5 1.0 5.0
2.0 6.8 8.3 2.0 9.7
1.7 6.3 7.9 1.7 9.0
2.0 6.3 8.3 2.0 9.6
2.0 7.1 9.2 2.0 10.3
1.0 3.0 4.3 1.0 5.1
1.0 3.4 4.8 1.0 5.4
1.0 3.4 4.7 1.0 5.5
0.5 3.0 4.2 0.5 4.7
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
LIMITS
Tamb = +25oC
VCC = +5.0V
CL = 50pF
RL = 500Ω
Min Typ Max
Tamb = –40 to +85oC
VCC = +5.0V ±10%
CL = 50pF
RL = 500Ω
Min Max
2.0 0.4
1.5 0.0
2.0
1.5
1.5 0.0
1.0 –0.2
1.5
1.0
UNIT
ns
ns
3.0 1.9 3.0 ns
1998 Jan 16
7
7페이지 | |||
구 성 | 총 16 페이지수 | ||
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부품번호 | 상세설명 및 기능 | 제조사 |
74ABT899 | 9-bit dual latch transceiver with 8-bit parity generator/checker 3-State | NXP Semiconductors |
74ABT899 | 9-Bit Latchable Transceiver with Parity Generator/Checker | Fairchild Semiconductor |
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