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부품번호 74ABT899CSC 기능
기능 9-Bit Latchable Transceiver with Parity Generator/Checker
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74ABT899CSC 데이터시트, 핀배열, 회로
November 1992
Revised January 1999
74ABT899
9-Bit Latchable Transceiver
with Parity Generator/Checker
General Description
The ABT899 is a 9-bit to 9-bit parity transceiver with trans-
parent latches. The device can operate as a feed-through
transceiver or it can generate/check parity from the 8-bit
data busses in either direction.
The ABT899 features independent latch enables for the A-
to-B direction and the B-to-A direction, a select pin for
ODD/EVEN parity, and separate error signal output pins for
checking parity.
Features
s Latchable transceiver with output sink of 64 mA
s Option to select generate parity and check or
“feed-through” data/parity in directions A-to-B or B-to-A
s Independent latch enables for A-to-B and B-to-A
directions
s Select pin for ODD/EVEN parity
s ERRA and ERRB output pins for parity checking
s Ability to simultaneously generate and check parity
s May be used in systems applications in place of the
543 and 280
s May be used in system applications in place of the
657 and 373 (no need to change T/R to check parity)
s Guaranteed output skew
s Guaranteed multiple output switching specifications
s Output switching specified for both 50 pF and
250 pF loads
s Guaranteed simultaneous switching noise level and
dynamic threshold performance
s Guaranteed latchup protection
s High impedance glitch free bus loading during entire
power up and power down cycle
s Nondestructive hot insertion capability
s Disable time less than enable time to avoid bus
contention
Ordering Code:
Order Number Package Number
Package Description
74ABT899CSC
M28B
28-Lead Small Outline Integrated Circuit (SOIC), MS-013, 0.300” Wide Body
74ABT899CMSA
MSA28
28-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
74ABT899CQC
V28A
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450” Square
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagrams
Pin Assignment
for PLCC
Pin Assignment for
SOIC and SSOP
© 1999 Fairchild Semiconductor Corporation DS011509.prf
www.fairchildsemi.com




74ABT899CSC pdf, 반도체, 판매, 대치품
Absolute Maximum Ratings(Note 2)
Storage Temperature
Ambient Temperature under Bias
Junction Temperature under Bias
Plastic
VCC Pin Potential to
Ground Pin
Input Voltage (Note 3)
Input Current (Note 3)
Voltage Applied to Any Output
in the Disable or Power-
Off State
in the HIGH State
Current Applied to Output
in LOW State (Max)
65°C to +150°C
55°C to +125°C
55°C to +150°C
0.5V to +7.0V
0.5V to +7.0V
30 mA to +5.0 mA
0.5V to +5.5V
0.5V to VCC
twice the rated IOL (mA)
DC Latchup Source Current
Over Voltage Latchup (I/O)
500 mA
10V
Recommended Operating
Conditions
Free Air Ambient Temperature
40°C to +85°C
Supply Voltage
+4.5V to +5.5V
Minimum Input Edge Rate (V/t)
Data Input
50 mV/ns
Enable Input
20 mV/ns
Note 2: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 3: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol
Parameter
VIH Input HIGH Voltage
VIL Input LOW Voltage
VCD Input Clamp Diode Voltage
VOH Output HIGH
Voltage
VOL Output LOW Voltage
VID Input Leakage Test
Min Typ
2.0
2.5
2.0
4.75
IIH Input HIGH Current
IBVI
IBVIT
IIL
Input HIGH Current
Breakdown Test
Input HIGH Current
Breakdown Test (I/O)
Input LOW Current
IIH + IOZH Output Leakage Current
IIL + IOZL Output Leakage Current
IOS
ICEX
IZZ
Output Short-Circuit Current
Output HIGH Leakage Current
Bus Drainage Test
100
ICCH
ICCL
ICCZ
ICCT
ICCD
Power Supply Current
Power Supply Current
Power Supply Current
Additional ICC/Input
Dynamic ICC: No Load
(Note 4)
Note 4: Guaranteed, but not tested.
Note 5: Add 3.75 mA for each ERR LOW.
Max
0.8
1.2
0.55
5
7
Units
V
V
V
V
V
V
µA
µA
VCC Conditions
Recognized HIGH Signal
Recognized LOW Signal
Min IIN = −18 mA (Non I/O Pins)
Min IOH = −3 mA, (An, Bn, APAR, BPAR)
IOH = −32 mA, (An, Bn, APAR, BPAR)
Min IOL = 64 mA, (An, Bn, APAR, BPAR)
0.0 IID = 1.9 µA, (Non-I/O Pins)
All Other Pins Grounded
Max VIN = 2.7V (Non-I/O Pins) (Note 4)
VIN = VCC (Non-I/O Pins)
Max VIN = 7.0V (Non-I/O Pins)
100 µA Max VIN = 5.5V (An, Bn, APAR, BPAR)
5
50
50
275
50
100
250
34
250
2.5
0.4
µA Max VIN = 0.5V (Non-I/O Pins) (Note 4)
VIN = 0.0V (Non-I/O Pins)
µA 0V–5.5V VOUT = 2.7V (An, Bn);
GAB and GBA = 2.0V
µA 0V–5.5V VOUT = 0.5V (An, Bn);
GAB and GBA = 2.0V
mA Max VOUT = 0V (An, Bn, APAR, BPAR)
µA Max VOUT = VCC (An, Bn, APAR, BPAR)
µA 0.0V VOUT = 5.5V (An, Bn, APAR, BPAR);
All Others GND
µA
mA
µA
mA
mA/MHz
Max All Outputs HIGH
Max All Outputs LOW, ERRA/B = HIGH (Note 5)
Max Outputs 3-STATE All Others at VCC or GND
Max VI = VCC 2.1V All Others at VCC or GND
Max Outputs Open
GAB or GBA = GND, LE = HIGH
Non-I/O = GND or VCC
One bit toggling, 50% duty cycle
www.fairchildsemi.com
4

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74ABT899CSC 전자부품, 판매, 대치품
Extended AC Electrical Characteristics
(SOIC and PLCC Package)
TA = +25°C
TA = −40°C to +85°C TA = −40°C to +85°C
VCC = +5.0V
VCC = 4.5V–5.5V
VCC = 4.5V–5.5V
Symbol
Parameter
CL = 50 pF
9 Outputs Switching
CL = 250 pF
CL = 250 pF
1 Output Switching 9 Outputs Switching
Units
(Note 9)
(Note 10)
(Note 11)
Min Typ Max Min Max Min Max
fTOGGLE
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
Max Toggle Frequency
Propagation Delay
An to Bn
Propagation Delay
APAR to BPAR
Propagation Delay
An, Bn to BPAR, APAR
Propagation Delay
An, Bn to ERRA, ERRB
Propagation Delay
APAR, BPAR to ERRA, ERRB
100 MHz
1.5 6.2 2.0 7.2 2.5 9.5
ns
1.5 6.2 2.0 7.2 2.5 9.5
1.5 6.8 2.0 8.0 2.5 10.0 ns
1.5 6.8 2.0 8.0 2.0 10.0
2.5
10.0 3.0 12.5 3.5 13.5
ns
2.5 10.0 3.0 12.5 3.5 13.5
(Note 13)
3.0 12.0
(Note 13)
3.0 12.0
ns
(Note 13)
2.0 9.0
2.0 9.0
(Note 13)
ns
tPLH Propagation Delay
tPHL ODD/EVEN to APAR, BPAR
tPLH Propagation Delay
tPHL ODD/EVEN to ERRA, ERRB
(Note 13)
(Note 13)
2.5 9.9
2.5 9.9
2.0 8.8
2.0 8.8
(Note 13)
(Note 13)
ns
ns
tPLH Propagation Delay
tPHL SEL to APAR, BPAR
tPLH Propagation Delay
tPHL LEA, LEB to Bn, An
tPLH Propagation Delay
tPHL LEA, LEB to BPAR, APAR
tPLH Propagation Delay
tPHL LEA, LEB to ERRA, ERRB
(Note 13)
1.5 5.7
1.5 5.7
1.5 9.5
1.5 9.5
(Note 13)
2.0 9.5
(Note 13)
2.0 9.5
2.0 7.9 2.5 10.0
2.0 7.9 2.5 10.0
2.0 12.0 2.5 13.0
2.0 12.0 2.5 13.0
2.0 11.5
(Note 13)
2.0 11.5
ns
ns
ns
ns
tPZH Output enable time
1.5 7.0 2.0 8.5 2.5 10.5
tPZL GBA or GAB to An,
1.5 7.0 2.0 8.5 2.5 10.5 ns
APAR or Bn, BPAR
tPHZ Output disable time
1.0 6.5
tPLZ GBA or GAB to An,
1.0
6.5 (Note 12)
(Note 12)
ns
APAR or Bn, BPAR
Note 9: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-
HIGH, HIGH-to-LOW, etc.).
Note 10: This specification is guaranteed but not tested. The limits represent propagation delay with 250 pF load capacitors in place of the 50 pF load capac-
itors in the standard AC load. This specification pertains to single output switching only.
Note 11: This specification is guaranteed but not tested. The limits represent propagation delays for all paths described switching in phase (i.e., all LOW-to-
HIGH, HIGH-to-LOW, etc.) with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load
Note 12: The 3-STATE delay time is dominated by the RC network (500, 250 pF) on the output and has been excluded from the datasheet.
Note 13: Not applicable for multiple output switching.
7 www.fairchildsemi.com

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부품번호상세설명 및 기능제조사
74ABT899CSC

9-Bit Latchable Transceiver with Parity Generator/Checker

Fairchild Semiconductor
Fairchild Semiconductor

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