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부품번호 | 74ACT109 기능 |
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기능 | Dual JK Positive Edge-Triggered Flip-Flop | ||
제조업체 | Fairchild Semiconductor | ||
로고 | |||
전체 12 페이지수
74AC109, 74ACT109
Dual JK Positive Edge-Triggered Flip-Flop
March 2007
tm
Features
■ ICC reduced by 50%
■ Outputs source/sink 24mA
■ ACT109 has TTL-compatible inputs
General Description
The AC/ACT109 consists of two high-speed completely
independent transition clocked JK flip-flops. The clocking
operation is independent of rise and fall times of the
clock waveform. The JK design allows operation as a
D-Type flip-flop (refer to AC/ACT74 data sheet) by
connecting the J and K inputs together.
Asynchronous Inputs:
– LOW input to SD (Set) sets Q to HIGH level
– LOW input to CD (Clear) sets Q to LOW level
– Clear and Set are independent of clock
– Simultaneous LOW on CD and SD makes both
Q and Q HIGH
Ordering Information
Order
Number
74AC109SC
74AC109SJ
74AC109MTC
Package
Number
M16A
M16D
MTC16
74ACT109SC
74AC109MTC
M16A
MTC16
74ACT109PC
N16E
Package Description
www.DataSheet4U.com
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
Connection Diagram
Pin Descriptions
Pin Names
J1, J2, K1, K2
CP1, CP2
CD1, CD2
SD1, SD2
Q1, Q2, Q1, Q2
Description
Data Inputs
Clock Pulse Inputs
Direct Clear Inputs
Direct Set Inputs
Outputs
FACT™ is a trademark of Fairchild Semiconductor Corporation.
©1988 Fairchild Semiconductor Corporation
74AC109, 74ACT109 Rev. 1.5
www.fairchildsemi.com
DC Electrical Characteristics for AC
Symbol
VIH
Parameter
Minimum HIGH
Level Input Voltage
VIL Maximum LOW
Level Input Voltage
VOH Minimum HIGH
Level Output Voltage
VOL Maximum LOW
Level Output Voltage
IIN(3)
IOLD
IOHD
ICC(3)
Maximum Input
Leakage Current
Minimum Dynamic
Output Current(2)
Maximum Quiescent
Supply Current
VCC
(V)
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
5.5
5.5
5.5
Conditions
VOUT = 0.1V
or VCC – 0.1V
VOUT = 0.1V
or VCC – 0.1V
IOUT = –50µA
VIN = VIL or VIH:
IOH = –12mA
IOH = –24mA
IOH = –24mA(1)
IOUT = 50µA
VIN = VIL or VIH:
IOL = 12mA
IOL = 24mA
IOL = 24mA(1)
VI = VCC, GND
TA = +25°C TA = –40°C to +85°C
Typ. Guaranteed Limits
1.5 2.1
2.1
2.25 3.15
3.15
2.75 3.85
3.85
1.5 0.9
0.9
2.25 1.35
1.35
2.75 1.65
1.65
2.99 2.9
2.9
4.49 4.4
4.4
5.49 5.4
5.4
Units
V
V
V
0.002
0.001
0.001
2.56
3.86
4.86
0.1
0.1
0.1
2.46
3.76
4.76
0.1
0.1
0.1
V
0.36
0.36
0.36
±0.1
0.44
0.44
0.44
±1.0
µA
VOLD = 1.65V Max.
VOHD = 3.85V Min.
VIN = VCC or GND
2.0
75
–75
20.0
mA
mA
µA
Notes:
1. All outputs loaded; thresholds on input associated with output under test.
2. Maximum test duration 2.0ms, one output loaded at a time.
3. IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC.
©1988 Fairchild Semiconductor Corporation
74AC109, 74ACT109 Rev. 1.5
4
www.fairchildsemi.com
4페이지 AC Electrical Characteristics for ACT
Symbol
Parameter
fMAX
tPLH
tPHL
tPLH
tPHL
Maximum Clock Frequency
Propagation Delay,
CPn to Qn or Qn
Propagation Delay,
CPn to Qn or Qn
Propagation Delay,
CDn or SDn to Qn or Qn
Propagation Delay
CDn or SDn to Qn or Qn
Note:
8. Voltage range 5.0 is 5.0V ± 0.5V
VCC (V)(8)
5.0
5.0
5.0
5.0
5.0
TA = +25°C,
CL = 50pF
Min. Typ. Max.
145 210
4.0 7.0 11.0
TA = –40°C to +85°C,
CL = 50pF
Min.
Max.
125
3.5 13.0
Units
MHz
ns
3.0 6.0 10.0
2.5
11.5 ns
2.5 5.5 9.5
2.0
10.5 ns
2.5 6.0 10.0
2.0
11.5 ns
AC Operating Requirements for ACT
Symbol
Parameter
tS Setup Time, HIGH or LOW,
Jn or Kn to CPn
tH Hold Time, HIGH or LOW,
Jn or Kn to CPn
tW Pulse Width,
CPn or CDn or SDn
trec Recovery Time,
CDn or SDn to CPn
Note:
9. Voltage range 5.0 is 5.0V ± 0.5V
VCC (V)(9)
5.0
5.0
5.0
5.0
TA = +25°C, TA = –40°C to +85°C,
CL = 50pF
CL = 50pF
Typ.
Guaranteed Minimum
0.5 2.0
2.5
Units
ns
0 2.0 2.0 ns
3.0 5.0 6.0 ns
–2.5 0
0 ns
Capacitance
Symbol
CIN
CPD
Parameter
Input Capacitance
Power Dissipation Capacitance
Conditions
VCC = OPEN
VCC = 5.0V
Typ.
4.5
35.0
Units
pF
pF
©1988 Fairchild Semiconductor Corporation
74AC109, 74ACT109 Rev. 1.5
7
www.fairchildsemi.com
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DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |