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PDF 74ACT1284MTC Data sheet ( Hoja de datos )
| Número de pieza | 74ACT1284MTC | |
| Descripción | IEEE 1284 Transceiver | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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June 1996
Revised November 2000
74ACT1284
IEEE 1284 Transceiver
General Description
The 74ACT1284 contains four non-inverting bidirectional
buffers and three non-inverting buffers with open Drain out-
puts and high drive capability on the B Ports. It is intended
to provide a standard signaling method for a bi-direction
parallel peripheral in an Extended Capabilities Port mode
(ECP).
The HD (active HIGH) input pin enables the B Ports to
switch from open Drain to a high drive totem pole output,
capable of sourcing 14 mA on all seven buffers. The DIR
input determines the direction of data flow on the bidirec-
tional buffers. DIR (active HIGH) enables data flow from
A Ports to B Ports. DIR (active LOW) enables data flow
from B Ports to A Ports.
Features
s TTL-compatible inputs
s A Ports have standard 4 mA totem pole outputs
s Typical input hysteresis of 0.5V
s B Port high drive source/sink capability of 14 mA
s Bidirectional non-inverting buffers
s Supports IEEE P1284 Level 1 and Level 2 signaling
standards for bidirectional parallel communications
between personal computers and printing peripherals
s B Port outputs in High Impedance mode during power
down
s Guaranteed 4000V minimum ESD protection
Ordering Code:
Order Number Package Number
Package Description
74ACT1284SC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74ACT1284MSA
MSA20
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
74ACT1284MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
Pin Descriptions
Pin Names
HD
DIR
A1 - A4
B1 - B4
A5 - A7
B5 - B7
Description
High Drive Enable input (Active HIGH)
Direction Control Input
Side A Inputs or Outputs
Side B Inputs or Outputs
Side A Inputs
Side B Outputs
FACT is a trademark of Fairchild Semiconductor Corporation.
© 2000 Fairchild Semiconductor Corporation DS011683
www.fairchildsemi.com
1 page  
AC Loading and Waveforms
tSLEW measures between 10% to 90% on the tPHL Transition
tSLEW measures between 10% to 90% on the tPLH Transition
FIGURE 1. Port A to B Propagation Delay Waveforms
FIGURE 2. B Output Test Load and Waveforms
FIGURE 3. B to A Direction Test Load and Waveforms for Outputs A1 - A4
FIGURE 4. A to B Direction Test Load and Waveforms for Open Drain B1 - B7
5 www.fairchildsemi.com
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| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet 74ACT1284MTC.PDF ] | |
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