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부품번호 | 61S6432 기능 |
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기능 | 64K x 32 SYNCHRONOUS PIPELINE STATIC RAM | ||
제조업체 | Integrated Silicon Solution Inc | ||
로고 | |||
전체 19 페이지수
IS61S6432
ISSI®
64K x 32 SYNCHRONOUS
PIPELINE STATIC RAM
JUNE 2001
FEATURES
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
control
• Pentium™ or linear burst sequence control using
MODE input
• Three chip enables for simple depth expansion
and address pipelining
• Common data inputs and data outputs
• Power-down control by ZZ input
• JEDEC 100-Pin TQFP and PQFP package
• Single +3.3V power supply
• Two Clock enables and one Clock disable to
eliminate multiple bank bus contention
• Control pins mode upon power-up:
– MODE in interleave burst mode
– ZZ in normal operation mode
These control pins can be connected to GNDQ
or VCCQ to alter their power-up state
• Industrial temperature available
DESCRIPTION
The ISSI IS61S6432 is a high-speed, low-power
synchronous static RAM designed to provide a burstable,
high-performance, secondary cache for the Pentium™,
680X0™, and PowerPC™ microprocessors. It is organized
as 65,536 words by 32 bits, fabricated with ISSI's advanced
CMOS technology. The device integrates a 2-bit burst
counter, high-speed SRAM core, and high-drive capability
outputs into a single monolithic circuit. All synchronous
inputs pass through registers controlled by a positive-edge-
triggered single clock input.
Write cycles are internally self-timed and are initiated by the
rising edge of the clock input. Write cycles can be from one
to four bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
BW1 controls DQ1-DQ8, BW2 controls DQ9-DQ16, BW3
controls DQ17-DQ24, BW4 controls DQ25-DQ32,
conditioned by BWE being LOW. A LOW on GW input would
cause all bytes to be written.
Bursts can be initiated with either ADSP (Address Status
Processor) or ADSC (Address Status Cache Controller)
input pins. Subsequent burst addresses can be generated
internally by the IS61S6432 and controlled by the ADV
(burst address advance) input pin.
Asynchronous signals include output enable (OE), sleep
mode input (ZZ), clock (CLK) and burst mode input (MODE).
A HIGH input on the ZZ pin puts the SRAM in the power-
down state. When ZZ is pulled LOW (or no connect), the
SRAM normally operates after three cycles of the wake-up
period. A LOW input, i.e., GNDQ, on MODE pin selects
LINEAR Burst. A VCCQ (or no connect) on MODE pin selects
INTERLEAVED Burst.
FAST ACCESS TIME
Symbol Parameter
-200(1)
tKQ CLK Access Time 4
tKC Cycle Time
5
— Frequency
200
Note:
1. ADVANCE INFORMATION ONLY.
-166
5
6
166
-133
5
7.5
133
-117
5
8.5
117
-5
5
10
100
-6
6
12
83
-7 -8 Unit
7 8 ns
13 15 ns
75 66 MHz
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. • 1-800-379-4774
Rev. B
06/28/01
1
IS61S6432
ISSI ®
TRUTH TABLE
Operation
Address
Used
CE1 CE2 CE3 ADSP ADSC ADV WRITE OE
DQ
Deselected, Power-down
None
H X X X L X X X High-Z
Deselected, Power-down
None
L L X L X X X X High-Z
Deselected, Power-down
None
L X H L X X X X High-Z
Deselected, Power-down
None
L L X H L X X X High-Z
Deselected, Power-down
None
L X H H L X X X High-Z
Read Cycle, Begin Burst External L H L L X X X L Q
Read Cycle, Begin Burst
External L H L L X X X H High-Z
Write Cycle, Begin Burst
External L H L H L X L X D
Read Cycle, Begin Burst External L H L H L X H L Q
Read Cycle, Begin Burst
External L H L H L X H H High-Z
Read Cycle, Continue Burst Next
XX X H H L H L Q
Read Cycle, Continue Burst Next
X X X H H L H H High-Z
Read Cycle, Continue Burst Next
HX X X H L H L Q
Read Cycle, Continue Burst Next
H X X X H L H H High-Z
Write Cycle, Continue Burst Next
XX X H HL
L XD
Write Cycle, Continue Burst Next
HX X X H L L X D
Read Cycle, Suspend Burst Current X X X H H H H L Q
Read Cycle, Suspend Burst Current X X X H H H H H High-Z
Read Cycle, Suspend Burst Current H X X X H H H L Q
Read Cycle, Suspend Burst Current H X X X H H H H High-Z
Write Cycle, Suspend Burst Current X X X H H H L X D
Write Cycle, Suspend Burst Current H X X X H H L X D
Notes:
1. All inputs except OE must meet setup and hold times for the Low-to-High transition of clock (CLK).
2. Wait states are inserted by suspending burst.
3. "X" means don't care. WRITE=L means any one or more byte write enable signals (BW1-BW4) and BWE are LOW or GW is
LOW. WRITE=H means all byte write enable signals are HIGH.
4. For a Write operation following a Read operation, OE must be HIGH before the input data required setup time and held HIGH
throughout the input data hold time.
5. ADSP LOW always initiates an internal READ at the Low-to-High edge of clock. A WRITE is performed by setting one or
more byte write enable signals and BWE LOW or GW LOW for the subsequent L-H edge of clock.
PARTIAL TRUTH TABLE
Function
READ
READ
WRITE Byte 1
WRITE All Bytes
WRITE All Bytes
GW BWE BW1 BW2 BW3 BW4
H H X X XX
H X H H HH
H L L H HH
X L L L LL
L X X X XX
PB Integrated Silicon Solution, Inc. • 1-800-379-4774
Rev.B
06/28/01
4페이지 IS61S6432
CAPACITANCE(1,2)
Symbol Parameter
Conditions
Max.
Unit
CIN Input Capacitance
VIN = 0V
6 pF
COUT
Input/Output Capacitance
VOUT = 0V
8 pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 3.3V.
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level
Output Load
Unit
0V to 3.0V
1.5 ns
1.5V
See Figures 1 and 2
ISSI ®
AC TEST LOADS
ZO = 50Ω
Output
Buffer
30 pF
50Ω
1.5V
Figure 1
3.3V
317 Ω
OUTPUT
5 pF
Including
jig and
scope
Figure 2
351 Ω
Integrated Silicon Solution, Inc. • 1-800-379-4774
Rev.B
06/28/01
7
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부품번호 | 상세설명 및 기능 | 제조사 |
61S6432 | 64K x 32 SYNCHRONOUS PIPELINE STATIC RAM | Integrated Silicon Solution Inc |
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