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PDF 62C1024L Data sheet ( Hoja de datos )
| Número de pieza | 62C1024L | |
| Descripción | 128K x 8 LOW POWER CMOS STATIC RAM | |
| Fabricantes | Integrated Silicon Solution Inc | |
| Logotipo |  |
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IS62C1024L
128K x 8 LOW POWER CMOS STATIC RAM
ISSI®
DECEMBER 2003
FEATURES
• High-speed access time: 35, 70 ns
• Low active power: 450 mW (typical)
• Low standby power: 150 µW (typical) CMOS
standby
• Output Enable (OE) and two Chip Enable
(CE1 and CE2) inputs for ease in applications
• Fully static operation: no clock or refresh
required
• TTL compatible inputs and outputs
• Single 5V (±10%) power supply
DESCRIPTION
The ISSI IS62C1024L is a low power,131,072-word by 8-bit
CMOS static RAM. It is fabricated using ISSI's high-performance
CMOS technology. This highly reliable process coupled
with innovative circuit design techniques, yields higher
performance and low power consumption devices.
When CE1 is HIGH or CE2 is LOW (deselected), the
device assumes a standby mode at which the power
dissipation can be reduced by using CMOS input levels.
Easy memory expansion is provided by using two Chip
Enable inputs, CE1 and CE2. The active LOW Write
Enable (WE) controls both writing and reading of the
memory.
The IS62C1024L is available in 32-pin plastic SOP and
TSOP (type 1) packages.
FUNCTIONAL BLOCK DIAGRAM
A0-A16
VDD
GND
I/O0-I/O7
DECODER
128K x 8
MEMORY ARRAY
I/O
DATA
CIRCUIT
COLUMN I/O
CE1
CE2 CONTROL
OE CIRCUIT
WE
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any
published information and before placing orders for products.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. E
11/26/03
1
1 page  
IS62C1024L
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level
Output Load
Unit
0V to 3.0V
5 ns
1.5V
See Figures 1a and 1b
AC TEST LOADS
480 Ω
5V
OUTPUT
100 pF
Including
jig and
scope
255 Ω
Figure 1a.
480 Ω
5V
OUTPUT
5 pF
Including
jig and
scope
Figure 1b.
255 Ω
ISSI ®
AC WAVEFORMS
READ CYCLE NO. 1(1,2)
ADDRESS
DOUT
tRC
tOHA
tAA
tOHA
DATA VALID
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. E
11/26/03
5
5 Page 
PACKAGING INFORMATION
Plastic TSOP-Type I
Package Code: T (32-pin)
1
ISSI®
EH
N
D
SEATING PLANE
SA
e
B A1
L
αC
MILLIMETERS
INCHES
Symbol Min. Max.
No. Leads
32
A — 1.20
A1 0.05 0.25
B 0.17 0.23
C 0.12 0.17
D 7.90 8.10
E 18.30 18.50
H 19.80 20.20
e 0.50 BSC
L 0.40 0.60
α 0° 8°
S 0.25 REF
Min. Max.
— 0.047
0.002 0.010
0.007 0.009
0.005 0.007
0.311 0.319
0.720 0.728
0.780 0.795
0.020 BSC
0.016 0.024
0° 8°
0.010 REF
Notes:
1. Controlling dimension: millimeters, unless
otherwise specified.
2. BSC = Basic lead spacing between centers.
3. Dimensions D and E do not include mold
flash protrusions and should be measured
from the bottom of the package.
4. Formed leads shall be planar with respect
to one another within 0.004 inches at the
seating plane.
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
06/13/03
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet 62C1024L.PDF ] | |
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