6812 Datasheet PDF - Allegro MicroSystems
| Part Number | 6812 | |
| Description | DABiC-IV/ 20-BIT SERIAL-INPUT/ LATCHED SOURCE DRIVER | |
| Manufacturers | Allegro MicroSystems | |
| Logo |  |
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6812
A6812xA
LOAD
SUPPLY
1
VBB
SERIAL
DATA OUT
2
OUT20 3
OUT19 4
OUT18 5
OUT 17 6
OUT 16 7
OUT15 8
OUT14 9
OUT13 10
OUT12 11
OUT11 12
BLANKING 13 BLNK
GROUND 14
VDD
28
LOGIC
SUPPLY
27
SERIAL
DATA IN
26 OUT 1
25 OUT 2
24 OUT 3
23 OUT 4
22 OUT5
21 OUT 6
20 OUT7
19 OUT8
18 OUT9
17 OUT 10
ST 2186 STROBE
CLK 2175 CLOCK
Dwg. PP-029-7
ABSOLUTE MAXIMUM RATINGS
at TA = 25°C
Logic Supply Voltage, VDD ................... 7.0 V
Driver Supply Voltage, VBB ................... 60 V
Continuous Output Current Range,
IOUT ......................... -40 mA to +15 mA
Input Voltage Range,
VIN ....................... -0.3 V to VDD + 0.3 V
Package Power Dissipation,
PD ........................................ See Graph
Operating Temperature Range, TA
(Suffix ‘E–’) .................. -40°C to +85°C
(Suffix ‘S–’) .................. -20°C to +85°C
Storage Temperature Range,
TS ............................... -55°C to +125°C
Caution: These CMOS devices have input static
protection (Class 2) but are still susceptible to
damage if exposed to extremely high static
electrical charges.
DABiC-IV, 20-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVER
The A6812– devices combine a 20-bit CMOS shift register,
accompanying data latches and control circuitry with bipolar sourcing
outputs and pnp active pull downs. Designed primarily to drive
vacuum-fluorescent displays, the 60 V and -40 mA output ratings also
allow these devices to be used in many other peripheral power driver
applications. The A6812– features an increased data input rate (com-
pared with the older UCN/UCQ5812-F) and a controlled output slew
rate.
The CMOS shift register and latches allow direct interfacing with
microprocessor-based systems. With a 3.3 V or 5 V logic supply, they
will operate to at least 10 MHz.
A CMOS serial data output permits cascade connections in applica-
tions requiring additional drive lines. Similar devices are available as
the A6809– and A6810– (10 bits), A6811– (12 bits), and A6818– (32
bits).
The A6812– output source drivers are npn Darlingtons, capable of
sourcing up to 40 mA. The controlled output slew rate reduces electro-
magnetic noise, which is an important consideration in systems that
include telecommunications and/or microprocessors and to meet
government emissions regulations. For inter-digit blanking, all output
drivers can be disabled and all sink drivers turned on with a BLANK-
ING input high. The pnp active pull-downs will sink at least 2.5 mA.
Two temperature ranges are available for optimum performance in
commercial (suffix S-) or industrial (suffix E-) applications. Package
styles are provided for through-hole DIP (suffix -A), surface-mount
SOIC (suffix -LW), or minimum-area surface-mount PLCC (suffix
-EP). Copper lead frames, low logic-power dissipation, and low
output-saturation voltages allow these drivers to source 25 mA from all
outputs continuously to more than +43°C (suffix -LW), +61°C (suffix
-EP), or +77°C (suffix -A).
FEATURES
I Controlled Output Slew Rate I Low Output-Saturation Voltages
I High-Speed Data Storage I Low-Power CMOS Logic
I 60 V Minimum
and Latches
Output Breakdown
I Improved Replacements
I High Data Input Rate
for TL5812–, UCN5812–,
I PNP Active Pull-Downs
and UCQ5812–
Complete part number includes a suffix to identify operating
temperature range (E- or S-) and package type (-A, -EP, or -LW).
Always order by complete part number, e.g., A6812SLW .
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6812
20-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVER
TIMING REQUIREMENTS and SPECIFICATIONS
(Logic Levels are VDD and Ground)
C
CLOCK
50%
SERIAL
DATA IN
SERIAL
DATA OUT
AB
DATA
50%
t p(CH-SQX)
50%
DE
DATA
STROBE
50%
BLANKING
OUT N
LOW = ALL OUTPUTS ENABLED
t p(STH-QH)
t p(STH-QL)
90%
DATA
10%
Dwg. WP-029
BLANKING
OUT N
HIGH = ALL OUTPUTS BLANKED (DISABLED)
50%
t en(BQ)
t dis(BQ)
tr
DATA
10%
tf
90%
A. Data Active Time Before Clock Pulse
(Data Set-Up Time), tsu(D) ...................................... 25 ns
B. Data Active Time After Clock Pulse
(Data Hold Time), th(D) ............................................ 25 ns
C. Clock Pulse Width, tw(CH) ............................................ 50 ns
D. Time Between Clock Activation and Strobe, tsu(C) .... 100 ns
E. Strobe Pulse Width, tw(STH) .......................................... 50 ns
NOTE – Timing is representative of a 10 MHz clock. Higher
speeds may be attainable with increased supply voltage;
operation at high temperatures will reduce the specified
maximum clock frequency.
Serial Data present at the input is transferred to the shift
register on the logic “0” to logic “1” transition of the CLOCK
input pulse. On succeeding CLOCK pulses, the registers shift
Dwg. WP-030
data information towards the SERIAL DATA OUTPUT. The
SERIAL DATA must appear at the input prior to the rising edge
of the CLOCK input waveform.
Information present at any register is transferred to the
respective latch when the STROBE is high (serial-to-parallel
conversion). The latches will continue to accept new data as
long as the STROBE is held high. Applications where the
latches are bypassed (STROBE tied high) will require that the
BLANKING input be high during serial data entry.
When the BLANKING input is high, the output source
drivers are disabled (OFF); the pnp active pull-down sink
drivers are ON. The information stored in the latches is not
affected by the BLANKING input. With the BLANKING input
low, the outputs are controlled by the state of their respective
latches.
www.allegromicro.com
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| Information | Total 10 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ 6812.PDF Datasheet ] | |
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