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6818 데이터시트 PDF




Allegro MicroSystems에서 제조한 전자 부품 6818은 전자 산업 및 응용 분야에서
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부품번호 6818 기능
기능 DABiC-IV/ 32-BIT SERIAL-INPUT/ LATCHED SOURCE DRIVER
제조업체 Allegro MicroSystems
로고 Allegro MicroSystems 로고


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6818 데이터시트, 핀배열, 회로
6818
A6818xA
LOAD
SUPPLY
1
VBB
SERIAL
DATA OUT
2
OUT 32 3
OUT 31 4
OUT 30 5
OUT 29 6
OUT 28 7
OUT27 8
OUT26 9
OUT25 10
OUT 24 11
OUT 23 12
OUT22 13
OUT21 14
OUT 20 15
OUT19 16
OUT 18 17
OUT17 18
BLANKING 19 BLNK
GROUND 20
VDD
40
LOGIC
SUPPLY
39
SERIAL
DATA IN
38 OUT 1
37 OUT 2
36 OUT 3
35 OUT 4
34 OUT5
33 OUT 6
32 OUT7
31 OUT8
30 OUT9
29 OUT 10
28 OUT 11
27 OUT 12
26 OUT 13
25 OUT 14
24 OUT 15
23 OUT 16
ST 22 STROBE
CLK 21 CLOCK
Dwg. PP-029-4
ABSOLUTE MAXIMUM RATINGS
at TA = 25°C
Logic Supply Voltage, VDD ................... 7.0 V
Driver Supply Voltage, VBB ................... 60 V
Continuous Output Current Range,
IOUT ......................... -40 mA to +15 mA
Input Voltage Range,
VIN ....................... -0.3 V to VDD + 0.3 V
Package Power Dissipation,
PD ........................................ See Graph
Operating Temperature Range, TA
(Suffix ‘E–’) .................. -40°C to +85°C
(Suffix ‘S–’) .................. -20°C to +85°C
Storage Temperature Range,
TS ............................... -55°C to +125°C
Caution: These CMOS devices have input
static protection (Class 2) but are still
susceptible to damage if exposed to
extremely high static electrical charges.
DABiC-IV, 32-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVER
The A6818– devices combine a 32-bit CMOS shift register,
accompanying data latches and control circuitry with bipolar sourcing
outputs and pnp active pull downs. Designed primarily to drive
vacuum-fluorescent displays, the 60 V and -40 mA output ratings also
allow these devices to be used in many other peripheral power driver
applications. The A6818– features an increased data input rate (com-
pared with the older UCN/UCQ5818–F) and a controlled output slew
rate.
The CMOS shift register and latches allow direct interfacing with
microprocessor-based systems. With a 3.3 V or 5 V logic supply,
typical serial-data input rates are up to 33 MHz.
A CMOS serial data output permits cascade connections in applica-
tions requiring additional drive lines. Similar devices are available as
the A6809– and A6810– (10 bits), A6811– (12 bits), and A6812– (20
bits).
The A6818– output source drivers are npn Darlingtons, capable of
sourcing up to 40 mA. The controlled output slew rate reduces electro-
magnetic noise, which is an important consideration in systems that
include telecommunications and/or microprocessors and to meet
government emissions regulations. For inter-digit blanking, all output
drivers can be disabled and all sink drivers turned on with a BLANK-
ING input high. The pnp active pull-downs will sink at least 2.5 mA.
Two temperature ranges are available for optimum performance in
commercial (suffix S-) or industrial (suffix E-) applications. Package
styles are provided for through-hole DIP (suffix -A) or minimum-area
surface-mount PLCC (suffix -EP). Copper lead frames, low logic-
power dissipation, and low output-saturation voltages allow these
devices to drive most multiplexed vacuum-fluorescent displays over
the maximum operating temperature range.
FEATURES
I Controlled Output Slew Rate I Low Output-Saturation Voltages
I High-Speed Data Storage I Low-Power CMOS Logic
I 60 V Minimum
and Latches
Output Breakdown
I Improved Replacements
I High Data Input Rate
for SN75518N, SN75518NF,
I PNP Active Pull-Downs
UCN5818, and UCQ5818
Complete part number includes a suffix to identify operating
temperature range (E- or S-) and package type (-A or -EP). Always
order by complete part number, e.g., A6818SEP .




6818 pdf, 반도체, 판매, 대치품
6818
32-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVER
ELECTRICAL CHARACTERISTICS at TA = +25°C (A6818S-) or over operating temperature
range (A6818E- and A6818K-), VBB = 60 V unless otherwise noted.
Characteristic
Symbol Test Conditions
Limits @ VDD = 3.3 V Limits @ VDD = 5 V
Mln. Typ. Max. Min. Typ. Max. Units
Output Leakage Current
Output Voltage
Output Pull-Down Current
Input Voltage
Input Current
Input Clamp Voltage
Serial Data Output Voltage
Maximum Clock Frequency
Logic Supply Current
Load Supply Current
Blanking-to-Output Delay
Strobe-to-Output Delay
Output Fall Time
Output Rise Time
ICEX
VOUT(1)
VOUT(0)
IOUT(0)
VIN(1)
VIN(0)
IIN(1)
IIN(0)
VIK
VOUT(1)
VOUT(0)
fc
IDD(1)
IDD(0)
IBB(1)
IBB(0)
tdis(BQ)
ten(BQ)
tp(STH-QL)
tp(STH-QH)
tf
tr
VOUT = 0 V
IOUT = -25 mA
IOUT = 1 mA
VOUT = 5 V to VBB
VIN = VDD
VIN = 0.8 V
IIN = -200 µA
IOUT = -200 µA
IOUT = 200 µA
All Outputs High
All Outputs Low
All Outputs High, No Load
All Outputs Low
CL = 30 pF, 50% to 50%
CL = 30 pF, 50% to 50%
RL = 2.3 k, CL 30 pF
RL = 2.3 k, CL 30 pF
RL = 2.3 k, CL 30 pF
RL = 2.3 k, CL 30 pF
<-0.1 -15
57.5 58.3
1.0 1.5
2.5 5.0
2.2
— — 1.1
<0.01 1.0
<-0.01 -1.0
-0.8 -1.5
2.8 3.05
0.15 0.3
10 33
0.25 0.75
0.25 0.75
4.5 9.0
0.2 20
0.7 2.0
1.8 3.0
0.7 2.0
1.8 3.0
2.4 12
2.4 12
<-0.1 -15
57.5 58.3
1.0 1.5
2.5 5.0
3.3 — —
— — 1.7
<0.01 1.0
<-0.01 -1.0
-0.8 -1.5
4.5 4.75
0.15 0.3
10 33
0.3 1.0
0.3 1.0
4.5 9.0
0.2 20
0.7 2.0
1.8 3.0
0.7 2.0
1.8 3.0
2.4 12
2.4 12
µA
V
V
mA
V
V
µA
µA
V
V
V
MHz
mA
mA
mA
µA
µs
µs
µs
µs
µs
µs
Output Slew Rate
dV/dt
RL = 2.3 k, CL 30 pF
4.0 20 4.0 20 V/µs
Clock-to-Serial Data Out Delay tp(CH-SQX) IOUT = ±200 µA
50 — — 50
ns
Negative current is defined as coming out of (sourcing) the specified device terminal.
Typical data is is for design information only and is at TA = +25°C.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000

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6818 전자부품, 판매, 대치품
6818
32-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVER
A6818EEP & A6818SEP
Dimensions in Inches
(controlling dimensions)
28
18
0.319
0.291
0.021
0.013
0.319
0.291
0.050
BSC
29
0.032
0.026
0.695
0.685
0.656
0.650
39
17
INDEX AREA
7
0.020
MIN
0.180
0.165
40 44 1 2
0.656
0.650
0.695
0.685
Dimensions in Millimeters
(for reference only)
28
6
Dwg. MA-005-44A in
18
8.10
7.39
0.533
0.331
8.10
7.39
1.27
BSC
29
0.812
0.661
17.65
17.40
16.662
16.510
39
17
INDEX AREA
7
0.51
MIN
4.57
4.20
40 44 1 2
16.662
16.510
17.65
17.40
NOTES: 1. Exact body and lead configuration at vendors option within limits shown.
2. Lead spacing tolerance is non-cumulative.
6
Dwg. MA-005-44A mm
www.allegromicro.com

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부품번호상세설명 및 기능제조사
681

RECTIFIERS ASSEMBLIES

Microsemi Corporation
Microsemi Corporation
681-1

RECTIFIERS ASSEMBLIES

Microsemi Corporation
Microsemi Corporation

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