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기능 MULTI.FUNCTION PERIPHERAL
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68901N04 데이터시트, 핀배열, 회로
MK68901
MULTI–FUNCTION PERIPHERAL
. 8 INPUT/OUTPUT PINS
Individually programmable direction
. Individual interrupt source capability
- Programmable edge selection
16 SOURCE INTERRUPT CONTROLLER
8 Internal sources
8 External sources
Individual source enable
Individual source masking
Programmable interrupt service modes
- Polling
- Vector generation
. - Optional In-service status
Daisy chaining capability
FOUR TIMERS WITH INDIVIDUALLY PRO-
GRAMMABLE PRESCALING
Two multimode timers
- Delay mode
- Pulse width measurement mode
- Event counter mode
Two delay mode timers
. Independent clock input
Time out output option
SINGLE CHANNEL USART
Full Duplex
Asynchronous to 65 kbps
Byte synchronous to 1 Mbps
Internal/External baud rate generation
DMA handshake signals
.. Modem control
Loop back mode
68000 BUS COMPATIBLE
48 PIN DIP OR 52 PIN PLCC
1
DPIP48
Figure 1 : Pin connections.
PLCC52
DESCRIPTION
The MK68901 MFP (Multi-Function Peripheral) is a
combination of many of the necessary peripheral
functions in a microprocessor system.
Included are :
Eight parallel I/O lines
Interrrupt controller for 16 sources
Four timers
Single channel full duplex USART
The use of the MFP in a system can significantly re-
duce chip count, thereby reducing system cost. The
MFP is completely 68000 bus compatible, and 24 di-
rectly addressable internal registers provide the ne-
MFP
December 1988
1/33




68901N04 pdf, 반도체, 판매, 대치품
MK68901
Figure 4 : Register Map.
Address Port N°.
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
10
11
12
13
14
15
16
17
Abbreviation
GPIP
AER
DDR
IERA
IERB
IPRA
IPRB
ISRA
ISRB
IMRA
IMRB
VR
TACR
TBCR
TCDCR
TADR
TBDR
TCDR
TDDR
SCR
UCR
RSR
TSR
UDR
Register Name
GENERAL PURPOSE I/O
ACTIVE EDGE REGISTER
DATA DIRECTION REGISTER
INTERRUPT ENABLE REGISTER A
INTERRUPT ENABLE REGISTER B
INTERRUPT PENDING REGISTER A
INTERRUPT PENDING REGISTER B
INTERRUPT IN-SERVICE REGISTER A
INTERRUPT IN-SERVICE REGISTER B
INTERRUPT MASK REGISTER A
INTERRUPT MASK REGISTER B
VECTOR REGISTER
TIMER A CONTROL REGISTER
TIMER B CONTROL REGISTER
TIMERS C AND D CONTROL REGISTER
TIMER A DATA REGISTER
TIMER B DATA REGISTER
TIMER C DATA REGISTER
TIMER D DATA REGISTER
SYNC CHARACTER REGISTER
USART CONTROL REGISTER
RECEIVER STATUS REGISTER
TRANSMITTER STATUS REGISTER
USART DATA REGISTER
INTERRUPTS
The General Purpose I/O-Interrupt Port (GPIP) pro-
vides eight I/O lines that may be operated either as
inputs or outputs under software control. In addition,
each line may generate an interrupt in either a po-
sitive going edge or a negative going edge of the in-
put signal.
The GPIP has three associated registers. One al-
lows the programmer to specify the Active Edge for
each bit that will trigger an interrupt. Another register
specifies the Data Direction (input or output) asso-
ciated with each bit. The third register is the actual
data I/O register used to input or output data to the
port. These three registers are illstrated in figure 5.
The Active Edge Register (AER) allows each of the
General Purpose Interrupts to provide an interrupt
on either a 1-0 transition or a 0-1 transition. Writing
a zero to the appropriate bit of the AER causes the
associated input to produce an interrupt on the 1-0
transition. The edge bit is simply one input to an ex-
clusive-or gate, with the other input coming from the
input buffer ant the output going to a 1-0 transition
detector. Thus, depending upon the state of the in-
put, writing the AER can cause an interrupt-produ-
cing transition, which will cause an interrupt on the
associated channel, if that channel is enabled. One
would then normally configure the AER before
enabling interrupts via IERA and IERB.
Note : Changing the edge bit, with the interrupt
enabled, may cause an interrupt on that channel.
The Data Direction Register (DDR) is used to define
10-17 as inputs or as outputs on a bit by bit basis.
Writing a zero into a bit of the DDR causes the cor-
responding Interrupt-I/O pin to be a Hi-Z input. Wri-
ting a one into a bit of the DDR causes the cor-
responding pin to be configured as a push-pull out-
put. When data is written into the GPIP, those pins
defined as inputs will remain in the Hi-Z state while
those pins defined as outputs will assume the state
(high or low) of their corresponding bit in the GPIP.
When the GPIP is read, the data read will come di-
rectly from the corresponding bit of the GPIPregister
for all pins defined as output, while the data read on
all pins defined as inputs will come from the input
buffers.
Each individual function in the MK68901 is provided
with a unique interrupt vector that is presented to the
system during the interrupt acknowledge cycle. The
interrupt vector returned during the interrupt ac-
knowledge cycle is shown in figure 6, while the vec-
tor register is shown in figure 7.
4/33

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68901N04 전자부품, 판매, 대치품
MK68901
Figure 9 : Interrupt Control Register Definitions
Priority
HIGHEST
LOWEST
Channel
1111
1110
1101
1100
1011
1010
1001
1000
0111
0110
0101
0100
0011
0010
0001
0000
Description
General Purpose Interrupt 7(I7)
General Purpose Interrupt 6(I6)
Timer A
Receive Buffer Full
Receive Error
Transmit Buffer Empty
Transmit Error
Timer B
General Purpose Interrupt 5(I5)
General Purpose Interrupt 4(I4)
Timer C
Timer D
General Purpose Interrupt 3(I3)
General Purpose Interrupt 2(I2)
General Purpose Interrupt 1(I1)
General Purpose Interrupt 0(I0)
Interrupts may be either polled or vectored. Each
channel may be individual enabled or disabled by
writing a one or a zero in the appropriate bit of Inter-
rupt Enable Registers (IERA, IERB - see figure 8 for
all registers in this section). When disabled, an in-
terrupt channel is completely inactive. Any internal
or external action which would normally produce an
interrupt on that channel is ignored and any pending
interrupt on that channel will be cleared by disabling
that channel. Disabling an interrupt channel has no
effect on the corresponding bit in Interrupt In-Ser-
vice Registers (ISRA, ISRB) ; thus, if the In-service
Registers are used and an interrupt is in service on
that channel when the channel is disabled, it will re-
main in service until cleared in the normal manner.
IERA and IERB are also readable.
When an interrupt is received on an enabled chan-
nel, its corresponding bit in the pending register will
be set. When that channel is acknowledged it will
pass its vector, and the corresponding bit in the In-
terrupt Pending Register (IPRA or IRPB) will be
cleared. IPRA and IPRB are readable ; thus by pol-
ling IPRA and IPRB, it can be determined whether
a channel has a pending interrupt. IPRA and IPRB
are also writeable and a pending interrupt can be
cleared without going through the acknowledge se-
quence by writing a zero to the appropriate bit. This
allows any one bit to be cleared, without altering any
other bits, simply by writing all ones except for the
bit position to be cleared to IPRA or IPRB. Thus a
fully polled interrupt scheme is possible. Note : wri-
ting a one to IPRA, IPRB has no effect on the inter-
rupt pending register.
The interrupt mask registers (IMRA and IMRB) may
be used to block a channel from making an interrupt
request. Writing a zero into the corresponding bit of
the mask register will still allow the channel to re-
ceive an interrupt and latch it into its pending bit (if
that channel is enabled), but will prevent that chan-
nel from making an interrupt request. If that channel
is causing an interrupt request at the time the cor-
responding bit in the mask register is cleared, the re-
quest will cease. If no other channel is making a re-
quest, INTR will go inactive. If the mask bit is re-en-
abled, any pending interrupt is now free to resume
its request unless blocked by a higher priority re-
quest for service. IMRA and IMRB are also readable
. A conceptual circuit of an interrupt channel is
shown in figure 10.
7/33

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