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73K224L-IH 데이터시트 PDF




ETC에서 제조한 전자 부품 73K224L-IH은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

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부품번호 73K224L-IH 기능
기능 V.22bis/V.22/V.21/ Bell 212A/Bell 103 Single-Chip Modem
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73K224L-IH 데이터시트, 핀배열, 회로
73K224L
V.22bis/V.22/V.21/ Bell 212A/Bell 103
Single-Chip Modem
DESCRIPTION
The 73K224L is a highly integrated single-chip
modem IC which provides the functions needed to
construct a V.22bis compatible modem, capable of
2400 bit/s full-duplex operation over dial-up lines. The
73K224L offers excellent performance and a high
level of functional integration in a single 28-pin DIP
and 44-pin TQFP package. This device supports
V.22bis, V.22, V.21, Bell 212A and Bell 103 modes of
operation, allowing both synchronous and
asynchronous communication. The 73K224L is
designed to appear to the systems designer as a
microprocessor peripheral, and will easily interface
with popular single-chip microprocessors (80C51
typical) for control of modem functions through its 8-
bit multiplexed address/data bus or via an optional
serial control bus. An ALE control line simplifies
address demultiplexing. Data communications
normally occur through a separate serial port. The
73K224L is pin and software compatible with the
73K212L and 73K222L single-chip modem ICs,
allowing system upgrades with a single component
change.
The 73K224L operates from a single +5V supply for
low power consumption.
The 73K224L is ideal for use in either free-standing or
integral system modem products where full-duplex
(continued)
BLOCK DIAGRAM
April 2000
FEATURES
One-chip multi-mode V.22bis/V.22/V.21 and Bell
212A/103 compatible modem data pump
FSK (300 bit/s), DPSK (600, 1200 bit/s), or QAM
(2400 bit/s) encoding
Pin and software compatible with other TDK
Semiconductor Corporation K-Series 1-chip
modems
Interfaces directly with standard microcontrollers
(80C51 typical)
Parallel microcontroller bus for modem control and
status monitoring functions
Selectable
asynch/synch
with
internal
buffer/debuffer and scrambler/descrambler
functions
All synchronous and asynchronous operating
modes (internal, external, slave)
Adaptive equalization for optimum performance
over all lines
Programmable transmit attenuation (16 dB, 1 dB
steps), selectable receive boost (+18 dB)
Call progress, carrier, answer tone, unscrambled
mark, S1, and signal quality monitors
DTMF, answer and guard tone generators
Test modes available: ALB, DL, RDL, Mark, Space,
Alternating bit, S1 pattern
CMOS technology for low power consumption
(typically 100 mW @ 5V) with power-down mode
(15 mW @ 5V)
TTL and CMOS compatible inputs and outputs




73K224L-IH pdf, 반도체, 판매, 대치품
73K224L
V.22bis/V.22/V.21/Bell 212A/Bell 103
Single-Chip Modem
PIN DESCRIPTION
POWER
NAME
GND
VDD
VREF
ISET
TYPE
I
I
O
I
DESCRIPTION
System Ground.
Power supply input, 5V -5% +10%. Bypass with 0.22 µF and 22 µF capacitors to
GND.
An internally generated reference voltage. Bypass with 0.22 µF capacitor to
GND.
Chip current reference. Sets bias current for op-amps. The chip current is set by
connecting this pin to VDD through a 2 Mresistor. Iset should be bypassed to
GND with a 0.22 µF capacitor.
PARALLEL MICROPROCESSOR INTERFACE
ALE
AD0- AD7
CS
I
I/O
/Tristate
I
Address latch enable. The falling edge of ALE latches the address on AD0-AD2
and the chip select on CS.
Address/data bus. These bidirectional tri-state multiplexed lines carry infor-
mation to and from the internal registers.
Chip select. A low on this pin allows a read cycle or a write cycle to occur. AD0-
AD7 will not be driven and no registers will be written if CS (latched) is not active.
CS is latched on the falling edge of ALE.
CLK
INT
RD
RESET
WR
O Output clock. This pin is selectable under processor control to be either the
crystal frequency (for use as a processor clock) or 16 x the data rate for use as a
baud rate clock in QAM/DPSK modes only. The pin defaults to the crystal
frequency on reset.
O Interrupt. This open drain /weak pull-up, output signal is used to inform the
processor that a detect flag has occurred. The processor must then read the
detect register to determine which detect triggered the interrupt. INT will stay
active until the processor reads the detect register or does a full reset.
I Read. A low requests a read of the 73K224L internal registers. Data cannot be
output unless both RD and the latched CS are active or low.
I Reset. An active high signal on this pin will put the chip into an inactive state. All
control register bits (CR0, CR1, CR2, CR3, Tone) will be reset. The output of the
CLK pin will be set to the crystal frequency. An internal pull down resistor permits
power on reset using a capacitor to VDD.
I Write. A low on this informs the 73K224L that data is available on AD0-AD7 for
writing into an internal register. Data is latched on the rising edge of WR. No data
is written unless both WR and the latched CS are active (low).
NOTE: The serial control mode is provided by tying ALE high and CS low. In this configuration AD7 becomes
DATA and AD0, AD1 and AD2 become the address only.
4

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73K224L-IH 전자부품, 판매, 대치품
73K224L
V.22bis/V.22/V.21/Bell 212A/Bell 103
Single-Chip Modem
REGISTER ADDRESS TABLE
ADDRESS
DATA BIT NUMBER
REGISTER
AD2 - AD0
D7
D6 D5
D4
D3
D2
D1
D0
CONTROL
REGISTER
0
CR0
000
MODULATION
OPTION
MODULATION
TYPE
1
MODULATION
TYPE
0
TRANSMIT
MODE
2
TRANSMIT
MODE
1
TRANSMIT
MODE
0
TRANSMIT
ENABLE
ANSWER/
ORIGINATE
CONTROL
REGISTER
1
CR1
QAM: 0=2400 BIT/S
DPSK: 0=1200 BIT/S
1=600 BIT/S
FSK: 0=103 MODE
1=V.21
TRANSMIT
001 PATTERN
1
10=QAM
00=DPSK
01=FSK
TRANSMIT
PATTERN
0
0000=PWR DOWN
0001=INT SYNCH
0010=EXT SYNCH
0011=SLAVE SYNCH
0100=ASYCH 8 BITS/CHAR
0101=ASYCH 9 BITS/CHAR
0110=ASYCH 10 BITS/CHAR
0111=ASYCH 11 BITS/CHAR
1X00=FSK
ENABLE
DETECT
INTERRUPT
BYPASS
SCRAMBLER
CLK
CONTROL
0=DISABLE
TXA OUTPUT
1=ENABLE
TXA OUTPUT
0=ANSWER
1=ORIGINATE
RESET
TEST
MODE
1
TEST
MODE
0
DETECT
REGISTER
DR
TONE
CONTROL
REGISTER
TR
00=TX DATA
01=TX ALTERNATE
10=TX MARK
11=TX SPACE
0=DISABLE
1=ENABLE
0=NORMAL
1=BYPASS
SCRAMBLER
0=XTAL
1=16 X DATA
RATE OUTPUT
AT CLK PIN IN
QAM/DPSK
MODE ONLY
0=NORMAL
1=RESET
00=NORMAL
01=ANALOG LOOPBACK
10=REMOTE DIGITAL
LOOPBACK
11=LOCAL DIGITAL
LOOPBACK
RECEIVE
UNSCR.
ANSWER
CP
SIGNAL
010
LEVEL
S1 PATTERN
RECEIVE
MARKS
CARRIER
TONE
TONE
QUALITY
INDICATOR
DETECT
DATA
DETECT
DETECT
DETECT
DETECT
INDICATOR
0=SIGNAL
BELOW
THRESHOLD
1=ABOVE
THRESHOLD
0=NOT PRESENT
1=PATTERN
FOUND
OUTPUTS
RECEIVED
DATA STREAM
0=CONDITION NOT DETECTED
1=CONDITION DETECTED
011
RXD
OUTPUT
CONTROL
TRANSMIT
GUARD
TONE
TRANSMIT
ANSWER
TONE
TRANSMIT
DTMF
DTMF3
DTMF2/
4 W/FDX
0=GOOD
1=BAD
DTMF1/
EXTENDED
OVERSPEED
DTMF0/
GUARD/
ANSWER/
CALLING/SCT
RXD PIN
0=NORMAL
1=OPEN
0=OFF
1=ON
0=OFF
1=ON
0=DATA
1=TX DTMF
4 BIT CODE FOR 1 OF 16
DUAL TONE COMBINATIONS
0=1800 Hz G.T.
2225 Hz ANS TONE
GENERATED
1= 550 Hz G.T.
2100 Hz ANS TONE
GENERATED &
DETECTED (V.21, V.22)
CONTROL
REGISTER
2
CR2
100
CONTROL
REGISTER
3
CR3
101
SPECIAL
REGISTER
SR
101
ID
REGISTER
10
110
00XX=73K212AL, 322L, 321L
01XX=73K221AL, 302L
10XX=73K222AL, 222BL
1100=73K224L
1110=73K324L
1100=73K224BL
1110=73K324BL
SPECIAL
CALL
TRANSMIT
RESET
TRAIN
EQUALIZER
0
REGISTER
INITIALIZE
S1
16 WAY
DSP
INHIBIT
ENABLE
ACCESS
0=ACCESS CR3
1=ACCESS
SPECIAL
REGISTER
0=DSP IN
DEMOD MODE
1=DSP IN CALL
PROGRESS
MODE
0=NORMAL
DOTTING
1=S1
0=RX=TX
1=RX=16 WAY
0=DSP
INACTIVE
1=DSP
ACTIVE
0=ADAPT EQ
ACTIVE
1=ADAPT EQ
FROZEN
0=ADAPT EQ
IN INIT
1=ADAPT EQ
OK TO ADAPT
TXDALT
ALTERNATE
TRANSMIT
DATA
SOURCE
TRISTATE
TX/RXCLK
0=NORMAL
1=TRISTATE
0
TX BAUD
CLOCK
RECEIVE
TRANSMIT
0
GAIN
ATTEN.
BOOST
3
0=NO BOOST
1=18 dB BOOST
RX UNSCR.
DATA
0
TXD
SOURCE
TRANSMIT
ATTEN.
2
TRANSMIT
ATTEN.
1
0000-1111, SETS
TRANSMIT ATTENUATOR
16 dB RANGE
DEFAULT=0100 ³ -10 dbM0
SQ
SELECT1
SQ
SELECT0
TRANSMIT
ATTEN.
0
0
OUTPUTS
TXBAUD
CLOCK
OUTPUTS
UNSCR.
DATA
0=TXD PIN
1=TXALT BIT
00³10 -5 BER
01³10 -6 BER
10³10 -4 BER
11³10 -3 BER
ID ID ID ID X X X X
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73K224L-IH

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