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PDF 74173 Data sheet ( Hoja de datos )
| Número de pieza | 74173 | |
| Descripción | Quad 3-State D Flip-Flop with Common Clock and Reset | |
| Fabricantes | Motorola Inc | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de 74173 (archivo pdf) en la parte inferior de esta página. Total 6 Páginas | ||
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Quad 3-State D Flip-Flop with
Common Clock and Reset
High–Performance Silicon–Gate CMOS
The MC74HC173 is identical in pinout to the LS173. The device inputs are
compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.
Data, when enabled, are clocked into the four D flip–flops with the rising
edge of the common Clock. When either or both of the Output Enable
Controls is high, the outputs are in a high–impedance state. This feature
allows the HC173 to be used in bus–oriented systems. The Reset feature is
asynchronous and active high.
• Output Drive Capability: 15 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity 208 FETs or 52 Equivalent Gates
LOGIC DIAGRAM
DATA
INPUTS
D0 14
D1 13
D2 12
D3 11
3 Q0
4 Q1
5 Q2
6 Q3
3–STATE
NONINVERTING
OUTPUTS
CLOCK 7
MC74HC173
16
1
16
1
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
D SUFFIX
SOIC PACKAGE
CASE 751B–05
ORDERING INFORMATION
MC74HCXXXN
MC74HCXXXD
Plastic
SOIC
PIN ASSIGNMENT
OE1
OE2
Q0
Q1
Q2
Q3
CLOCK
GND
1
2
3
4
5
6
7
8
16 VCC
15 RESET
14 D0
13 D1
12 D2
11 D3
10 DE2
9 DE1
DATA–
ENABLES
DE1 9
DE2 10
RESET 15
OUTPUT OE1 1
ENABLES OE2 2
VCC = PIN 16
GND = PIN 8
Output Enables
OE1 OE2
LL
LL
LL
LL
LL
LL
LL
LL
LH
HL
HH
Reset
H
L
L
L
L
L
L
L
X
X
X
FUNCTION TABLE
Inputs
Data Enables
Clock DE1 DE2
XXX
LXX
HXX
HX
XH
LL
LL
XX
XXX
XXX
XXX
Output
Data
D
X
X
X
X
X
L
H
X
X
X
X
Q
L
No Change
No Change
No Change
No Change
L
H
No Change
High Impedance
High Impedance
High Impedance
10/95
© Motorola, Inc. 1995
1 REV 6
1 page  
DEVICE
UNDER
TEST
TEST POINT
OUTPUT
CL*
* Includes all probe and jig capacitance
Figure 5.
D0 14
13
D1
DATA
INPUTS
12
D2
D3 11
DATA– DE1 9
ENABLES DE2 10
RESET 15
CLOCK 7
OUTPUT
ENABLES
OE1 1
OE2 2
TEST CIRCUITS
DEVICE
UNDER
TEST
TEST POINT
OUTPUT 1 kΩ
CL *
MC74HC173
CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ and tPZH.
* Includes all probe and jig capacitance
Figure 6.
LOGIC DETAIL
DQ
C
C
R
DQ
C
C
R
DQ
C
C
R
DQ
C
C
R
VCC
3 Q0
VCC
4 Q1
VCC
5 Q2
VCC
6 Q3
High–Speed CMOS Logic Data
DL129 — Rev 6
5
MOTOROLA
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet 74173.PDF ] | |
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