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부품번호 74221 기능
기능 Dual Non-Retriggerable Monostable Multivibrator
제조업체 Fairchild Semiconductor
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74221 데이터시트, 핀배열, 회로
September 1983
Revised February 1999
MM74HC221A
Dual Non-Retriggerable Monostable Multivibrator
General Description
The MM74HC221A high speed monostable multivibrators
(one shots) utilize advanced silicon-gate CMOS technol-
ogy. They feature speeds comparable to low power Schot-
tky TTL circuitry while retaining the low power and high
noise immunity characteristic of CMOS circuits.
Each multivibrator features both a negative, A, and a posi-
tive, B, transition triggered input, either of which can be
used as an inhibit input. Also included is a clear input that
when taken low resets the one shot. The MM74HC221A
can be triggered on the positive transition of the clear while
A is held LOW and B is held HIGH.
The MM74HC221A is a non-retriggerable, and therefore
cannot be retriggered until the output pulse times out.
Pulse width stability over a wide range of temperature and
supply is achieved using linear CMOS techniques. The out-
put pulse equation is simply: PW = (REXT) (CEXT); where
PW
is in seconds, R is in ohms, and C is in farads. All inputs
are protected from damage due to static discharge by
diodes to VCC and ground.
Features
s Typical propagation delay: 40 ns
s Wide power supply range: 2V–6V
s Low quiescent current: 80 µA maximum (74HC Series)
s Low input current: 1 µA maximum
s Fanout of 10 LS-TTL loads
s Simple pulse width formula T = RC
s Wide pulse range: 400 ns to (typ)
s Part to part variation: ±5% (typ)
s Schmitt Trigger A & B inputs enable infinite signal input
rise or fall times
Ordering Code:
Order Number Package Number
Package Description
MM74HC221AM
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
MM74HC221ASJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC221AMTC
MTC16
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC221AN
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), MS-001, 0.300” Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagrams
Pin Assignments for DIP, SOIC, SOP and TSSOP
Timing Component
Top View
Note: Pin 6 and Pin 14 must be hard-wired to GND.
© 1999 Fairchild Semiconductor Corporation DS005325.prf
www.fairchildsemi.com




74221 pdf, 반도체, 판매, 대치품
AC Electrical Characteristics
VCC = 5V, TA = 25°C, CL = 15 pF, tr = tf = 6 ns
Symbol
Parameter
Conditions
tPLH
tPHL
tPHL
tPLH
tW
tREM
tWQ(MIN)
tWQ
Maximum Trigger Propagation
Delay A, B or Clear to Q
Maximum Trigger Propagation
Delay A, B or Clear to Q
Maximum Propagation Delay Clear to Q
Maximum Propagation Delay Clear to Q
Minimum Pulse Width A, B or Clear
Minimum Clear Removal Time
Minimum Output Pulse Width
Output Pulse Width
CEXT = 28 pF
REXT = 2 k
CEXT = 1000 pF
REXT = 10 k
Guaranteed
Typ Units
Limit
22 36 ns
25 42 ns
20 31
22 33
14 26
0
400
ns
ns
ns
ns
ns
10 µs
AC Electrical Characteristics
CL = 50 pF, tr = tf = 6 ns (unless otherwise specified)
Symbol
Parameter
Conditions
VCC TA = 25°C
Typ
TA = −40 to 85°C TA = −55 to 125°C
Units
Guaranteed Limits
tPLH Maximum Trigger Propagation
Delay A, B or Clear to Q
2.0V
4.5V
77
26
169
42
194
51
210 ns
57 ns
6.0V
21
32
39
44 ns
tPHL Maximum Trigger Propagation
Delay A, B or Clear to Q
2.0V
4.5V
88
29
197
48
229
60
250 ns
67 ns
6.0V
24
38
46
51 ns
tPHL Maximum Propagation
Delay Clear to Q
2.0V
4.5V
54
23
114
34
132
41
143 ns
45 ns
6.0V
19
28
33
36 ns
tPLH Maximum Propagation
Delay Clear to Q
2.0V
4.5V
56
25
116
36
135
42
147 ns
46 ns
6.0V
20
29
34
37 ns
tW Minimum Pulse Width
A, B, Clear
2.0V
4.5V
57
17
123
30
144
37
157 ns
42 ns
6.0V
12
21
27
30 ns
tREM
Minimum Clear
Removal Time
2.0V
4.5V
00
00
0 ns
0 ns
6.0V
00
0 ns
tTLH, tTHL Maximum Output
Rise and Fall Time
2.0V
4.5V
30
8
75
15
95
19
110 ns
22 ns
6.0V
7
13
16
19 ns
tWQ(MIN) Minimum Output
Pulse Width
tWQ Output Pulse Width
CEXT = 28 pF
REXT = 2 k
REXT = 6 k(VCC = 2V)
CEXT = 0.1 µF Min
REXT = 10 k
Max
2.0V
4.5V
6.0V
5.0V
5.0V
1.5
450
380
1
1
0.9
1.1
0.86
1.14
0.85
1.15
µs
ns
ns
ms
ms
CPD Power Dissipation
Capacitance (Note 5)
87
pF
CIN Maximum Input
Capacitance (Pins 7 & 15)
12 20
20
20 pF
CIN Maximum Input
Capacitance (other inputs)
6 10
10
10 pF
Note 5: CPD determines the no load dynamic power consumption, PD = CPD VCC2f + ICC VCC, and the no load dynamic current consumption,
IS = CPD VCCf + ICC.
www.fairchildsemi.com
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74221 전자부품, 판매, 대치품
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
Package Number M16A
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D
7 www.fairchildsemi.com

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