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IDT71256SA20PZ 데이터시트 PDF




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부품번호 IDT71256SA20PZ 기능
기능 CMOS STATIC RAM 256K (32K x 8-BIT)
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IDT71256SA20PZ 데이터시트, 핀배열, 회로
Integrated Device Technology, Inc.
CMOS STATIC RAM
256K (32K x 8-BIT)
IDT71256SA
FEATURES:
• 32K x 8 advanced high-speed CMOS static RAM
• Commercial (0° to 70°C) and Industrial (-40° to 85°C)
temperature options
• Equal access and cycle times
— Commercial: 12/15/20/25ns
— Industrial: 15/20ns
• One Chip Select plus one Output Enable pin
• Bidirectional data inputs and outputs directly
TTL-compatible
• Low power consumption via chip deselect
• Commercial product available in 28-pin 300- and 600-mil
Plastic DIP, 300 mil Plastic SOJ and TSOP packages
• Industrial product available in 28-pin 300 mil Plastic SOJ
and TSOP packages
DESCRIPTION:
The ID71256SA is a 262,144-bit high-speed Static RAM
organized as 32K x 8. It is fabricated using IDT’s high-
perfomance, high-reliability CMOS technology. This state-of-
the-art technology, combined with innovative circuit design
techniques, provides a cost-effective solution for high-speed
memory needs.
The IDT71256SA has an output enable pin which operates
as fast as 6ns, with address access times as fast as 12ns. All
bidirectional inputs and outputs of the IDT71256SA are TTL-
compatible and operation is from a single 5V supply. Fully
static asynchronous circuitry is used, requiring no clocks or
refresh for operation.
The IDT71256SA is packaged in 28-pin 300- and 600-mil
Plastic DIP, 28-pin 300 mil Plastic SOJ and TSOP.
FUNCTIONAL BLOCK DIAGRAM
A0
A1
A2
A3
A4
A5
A6 ADDRESS
A7
A8 DECODER
A9
A10
A11
A12
A13
A14
I/O 0 – I/O7 8
8
262,144-BIT
MEMORY
ARRAY
I/O CONTROL
CS CONTROL
WE LOGIC
OE
2948 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES
©1997 Integrated Device Technology, Inc.
MAY 1997
DSC-2948/04
1




IDT71256SA20PZ pdf, 반도체, 판매, 대치품
IDT71256SA
CMOS STATIC RAM 256K (32K x 8-BIT)
INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ± 10%)
71256SA12(2) 71256SA15
71256SA20
Symbol
Parameter
Read Cycle
tRC Read Cycle Time
tAA Address Access Time
tACS
tCLZ(1)
tCHZ(1)
Chip Select Access Time
Chip Select to Output in Low-Z
Chip Deselect to Output in High-Z
tOE
tOLZ(1)
tOHZ(1)
Output Enable to Output Valid
Output Enable to Output in Low-Z
Output Disable to Output in High-Z
tOH
tPU(1)
tPD(1)
Output Hold from Address Change
Chip Select to Power Up Time
Chip Deselect to Power Down Time
Write Cycle
tWC Write Cycle Time
tAW Address Valid to End of Write
tCW Chip Select to End of Write
Min. Max. Min. Max. Min. Max.
12 — 15 — 20 —
— 12 — 15 — 20
— 12 — 15 — 20
4—4—4—
0 6 0 7 0 10
— 6 — 7 — 10
0—0—0—
060608
3—3—3—
0—0—0—
— 12 — 15 — 20
12 — 15 — 20 —
9 — 10 — 15 —
9 — 10 — 15 —
tAS
tWP
tWR
tDW
tDH
tOW(1)
tWHZ(1)
Address Set-up Time
Write Pulse Width
Write Recovery Time
Data Valid to End of Write
Data Hold Time
Output Active from End of Write
Write Enable to Output in High-Z
0—0—0—
9 — 10 — 15 —
0—0—0—
6 — 7 — 11 —
0—0—0—
4—4—4—
0 6 0 6 0 10
NOTE:
1. This parameter is guaranteed with the AC Load (Figure 2) by device characterization, but is not production tested.
2. Commercial temperature range only.
71256SA25(2)
Min. Max.
25 — ns
— 25 ns
— 25 ns
4 — ns
0 11 ns
— 11 ns
0 — ns
0 10 ns
3 — ns
0 — ns
— 25 ns
25 — ns
20 — ns
20 — ns
0 — ns
20 — ns
0 — ns
13 — ns
0 — ns
4 — ns
0 11 ns
2948 tbl 08
TIMING WAVEFORM OF READ CYCLE NO. 1(1)
ADDRESS
tAA
tRC
OE
CS
DATAOUT
VCC SUPPLY ICC
CURRENT
ISB
tOLZ (5)
tACS (3)
tCLZ (5)
HIGH IMPEDANCE
tPU
tOE
tOHZ (5)
tCHZ (5)
DATA OUT VALID
tPD
2948 drw 05
4

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IDT71256SA20PZ

CMOS STATIC RAM 256K (32K x 8-BIT)

Integrated Device Technology
Integrated Device Technology

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