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PDF KM4132G271B Data sheet ( Hoja de datos )
| Número de pieza | KM4132G271B | |
| Descripción | 128K x 32bit x 2 Banks Synchronous Graphic RAM LVTTL | |
| Fabricantes | Samsung semiconductor | |
| Logotipo |  |
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KM4132G271B
CMOS SGRAM
8Mbit SGRAM
128K x 32bit x 2 Banks
Synchronous Graphic RAM
LVTTL
Revision 2.4
May 1998
Samsung Electronics reserves the right to change products or specification without notice.
- 1 - Rev. 2.4 (May 1998)
1 page  
KM4132G271B
CMOS SGRAM
PIN CONFIGURATION DESCRIPTION
PIN
CLK
CS
NAME
System Clock
Chip Select
INPUT FUNCTION
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQMi
CKE
Clock Enable
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one clock +tSS prior to new command.
Disable input buffers for power down in standby.
A0 ~ A8
A9(BA)
RAS
CAS
WE
DQMi
DQi
DSF
VDD /VSS
VDDQ /VSSQ
N.C
Address
Bank Select Address
Row Address Strobe
Column Address Strobe
Write Enable
Data Input/Output Mask
Data Input/Output
Define Special Function
Power Supply /Ground
Data Output Power /Ground
No Connection
Row / Column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA8, Column address : CA0 ~ CA7
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK withRAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK withCAS low.
Enables column access.
Enables write operation and Row precharge.
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active.(Byte Masking)
Data inputs/outputs are multiplexed on the same pins.
Enables write per bit, block write and special mode register set.
Power Supply : +3.3V±0.3V/Ground
Provide isolated Power/Ground to DQs for improved noise immunity.
- 5 - Rev. 2.4 (May 1998)
5 Page 
KM4132G271B
SIMPLIFIED TRUTH TABLE
CMOS SGRAM
3. Auto refresh functions as same as CBR refresh of DRAM.
The automatical precharge without Row precharge command is meant by "Auto".
Auto/Self refresh can be issued only at both precharge state.
4. A9 : Bank select address.
If "Low" at read, (block) write, Row active and precharge, bank A is selected.
If "High" at read, (block) write, Row active and precharge, bank B is selected.
If A8 is "High" at Row precharge, A9 is ignored and both banks are selected.
5. It is determined at Row active cycle.
whether Normal/Block write operates in write per bit mode or not.
For A bank write, at A bank Row active, for B bank write, at B bank Row active.
Terminology : Write per bit =I/O mask
(Block) Write with write per bit mode=Masked(Block) Write
6. During burst read or write with auto precharge, new read/(block) write command cannot be issued.
Another bank read/(block) write command can be issued attRP after the end of burst.
7. Burst stop command is valid only at full page burst length.
8. DQM sampled at positive going edge of a CLK.
masks the data-in at the very CLK(Write DQM latency is 0)
but makes Hi-Z state the data-out of 2 CLK cycles after.(Read DQM latency is 2)
9. Graphic features added to SDRAM′s original features.
If DSF is tied to low, graphic functions are disabled and chip operates as a 8M SDRAM with 32 DQ′s.
SGRAM vs SDRAM
Function
DSF
SGRAM
Function
MRS
LH
MRS
SMRS
Bank Active
LH
Bank Active
with
Write per bit
Disable
Bank Active
with
Write per bit
Enable
If DSF is low, SGRAM functionality is identical to SDRAM functionality .
SGRAM can be used as an unified memory by the appropriate DSF control
--> SGRAM=Graphic Memory + Main Memory
Write
LH
Normal
Write
Block
Write
- 11 Rev. 2.4 (May 1998)
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet KM4132G271B.PDF ] | |
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