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KM416C1200B 데이터시트 PDF




Samsung semiconductor에서 제조한 전자 부품 KM416C1200B은 전자 산업 및 응용 분야에서
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부품번호 KM416C1200B 기능
기능 1M x 16Bit CMOS Dynamic RAM with Fast Page Mode
제조업체 Samsung semiconductor
로고 Samsung semiconductor 로고


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KM416C1200B 데이터시트, 핀배열, 회로
KM416C1000B, KM416C1200B
KM416V1000B, KM416V1200B
CMOS DRAM
1M x 16Bit CMOS Dynamic RAM with Fast Page Mode
DESCRIPTION
This is a family of 1,048,576 x 16 bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory
cells within the same row. Power supply voltage (+5.0V or +3.3V), refresh cycle (1K Ref. or 4K Ref.), access time (-5,-6 or -7), power
consumption(Normal or Low power) and package type(SOJ or TSOP-II) are optional features of this family. All of this family have CAS-
before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-version. This
1Mx16 Fast Page Mode DRAM family is fabricated using Samsung's advanced CMOS process to realize high band-width, low power
consumption and high reliability. It may be used as graphic memory unit for microcomputer, personal computer and portable machines.
FEATURES
¡Ü Part Identification
- KM416C1000B/B-L (5V, 4K Ref.)
- KM416C1200B/B-L (5V, 1K Ref.)
- KM416V1000B/B-L (3.3V, 4K Ref.)
- KM416V1200B/B-L (3.3V, 1K Ref.)
¡Ü Active Power Dissipation
Speed
-5
-6
-7
3.3V
4K 1K
396 576
360 540
324 504
Unit : mW
5V
4K 1K
605 880
550 825
495 770
¡Ü Refresh Cycles
Part
VCC
NO.
C1000B
V1000B
C1200B
V1200B
5V
3.3V
5V
3.3V
Refresh
cycle
4K
1K
Refresh period
Normal L-ver
64ms
16ms
128ms
¡Ü Perfomance Range
Speed
-5
-6
tRAC
50ns
60ns
tCAC
15ns
15ns
-7 70ns 20ns
tRC
90ns
110ns
130ns
tPC
35ns
40ns
45ns
Remark
5V/3.3V
5V/3.3V
5V/3.3V
¡Ü Fast Page Mode operation
¡Ü 2 CAS Byte/Word Read/Write operation
¡Ü CAS-before-RAS refresh capability
¡Ü RAS-only and Hidden refresh capability
¡Ü Self-refresh capability (L-ver only)
¡Ü TTL(5V)/LVTTL(3.3V) compatible inputs and outputs
¡Ü Early Write or output enable controlled write
¡Ü JEDEC Standard pinout
¡Ü Available in 42-pin SOJ 400mil and 50(44)-pin TSOP(II)
400mil packages
¡Ü Single +5V¡¾10% power supply (5V product)
¡Ü Single +3.3V¡¾0.3V power supply (3.3V product)
FUNCTIONAL BLOCK DIAGRAM
RAS
UCAS
LCAS
W
A0-A11
(A0 - A9)*1
A0 - A7
(A0 - A9)*1
Control
Clocks
VBB Generator
Refresh Timer
Refresh Control
Refresh Counter
Row Address Buffer
Col. Address Buffer
Row Decoder
Memory Array
1,048,576 x16
Cells
Column Decoder
Vcc
Vss
Lower
Data in
Buffer
Lower
Data out
Buffer
Upper
Data in
Buffer
Upper
Data out
Buffer
Note) *1 : 1K Refresh
DQ0
to
DQ7
OE
DQ8
to
DQ15
SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.




KM416C1200B pdf, 반도체, 판매, 대치품
KM416C1000B, KM416C1200B
KM416V1000B, KM416V1200B
CMOS DRAM
DC AND OPERATING CHARACTERISTICS (Continued)
Symbol
Power
ICC1 Don't care
Speed
-5
-6
-7
KM416V1000B
110
100
90
Max
KM416V1200B KM416C1000B
160 110
150 100
140 90
ICC2
Normal
L
Don't care
2
1
2
1
2
1
-5 110 160 110
ICC3 Don't care
-6
100
150
100
-7 90 140 90
-5 100 100 100
ICC4 Don't care
-6
90
90
90
-7 80 80 80
ICC5
Normal
L
Don't care
1
200
1
200
1
200
-5 110 160 110
ICC6 Don't care
-6
100
150
100
-7 90 140 90
ICC7 L Don't care 400 300 450
ICCS
L Don't care 200
200
250
KM416C1200B
160
150
140
2
1
160
150
140
100
90
80
1
200
160
150
140
350
250
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
uA
mA
mA
mA
uA
uA
ICC1* : Operating Current (RAS and UCAS, LCAS cycling @tRC=min.)
ICC2 : Standby Current (RAS=UCAS=LCAS=W=VIH)
ICC3* : RAS-only Refresh Current (UCAS=LCAS=VIH, RAS cycling @tRC=min.)
ICC4* : Fast Page Mode Current (RAS=VIL, UCAS or LCAS, Address cycling @tPC=min.)
ICC5 : Standby Current (RAS=UCAS=LCAS=W=VCC-0.2V)
ICC6* : CAS-Before-RAS Refresh Current (RAS, UCAS or LCAS cycling @tRC=min.)
ICC7 : Battery back-up current, Average power supply current, Battery back-up mode
Input high voltage(VIH)=VCC-0.2V, Input low voltage(VIL)=0.2V, UCAS, LCAS=0.2V,
Din=Don't care, TRC=31.25us(4K/L-ver), 125us(1K/L-ver),
TRAS=TRASmin~300ns
ICCS : Self Refresh Current
RAS=UCAS=LCAS=VIL, W=OE=A0 ~ A11=VCC-0.2V or 0.2V,
DQ0 ~ DQ15=VCC-0.2V, 0.2V or Open
*Note : ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open.
ICC is specified as an average current. In ICC1, ICC3 and ICC6, address can be changed maximum once while RAS=VIL. In ICC4,
address can be changed maximum once within one fast page mode cycle time, tPC.

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KM416C1200B 전자부품, 판매, 대치품
KM416C1000B, KM416C1200B
KM416V1000B, KM416V1200B
CMOS DRAM
NOTES
1. An initial pause of 200us is required after power-up followed by any 8 ROR or CBR cycles before proper device operation is
achieved.
2. Input voltage levels are Vih/Vil. VIH(min) and VIL(max) are reference levels for measuring timing of input signals.
Transition times are measured between VIH(min) and VIL(max) and are assumed to be 5ns for all inputs.
3. Measured with a load equivalent to 2 TTL(5V)/1TTL(3.3V) loads and 100pF.
4. Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only.
If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC.
5. This parameter defines the time at which the output achieves the open circuit condition and is not referenced to Voh or Vol.
6. tWCS, tRWD, tCWD, tAWD and tCPWD are non restrictive operating parameters. They are included in the data sheet as electrical
characteristics only. If tWCS¡ÃtWCS(min), the cycles is an early write cycle and the data output will remain high impedance for
the duration of the cycle. If tCWD¡ÃtCWD(min), tRWD¡ÃtRWD(min), tAWD¡ÃtAWD(min) and tCPWD¡ÃtCPWD(min), then the cycle is a
read-modify-write cycle and the data output will contain the data read from the selected address. If neither of the above condi-
tions is satisfied, the condition of the data out is indeterminate.
7. Either tRCH or tRRH must be satisfied for a read cycle.
8. These parameters are referenced to the CAS leading edge in ealy write cycles and to the W falling edge in OE controlled write
cycle and read-modify-write cycles.
9. Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as a reference point only. If
tRAD is greater than the specified tRAD(max) limit, then access time is controlled by tAA.
KM416C/V10(2)00B/BL Truth Table
RAS
LCAS
UCAS
W
HXXX
L HHX
L LHH
LHLH
L L LH
L LHL
LHL L
LLLL
L L LH
OE
X
X
L
L
L
H
H
H
H
DQ0 - DQ7
Hi-Z
Hi-Z
DQ-OUT
Hi-Z
DQ-OUT
DQ-IN
-
DQ-IN
Hi-Z
DQ8-DQ15
Hi-Z
Hi-Z
Hi-Z
DQ-OUT
DQ-OUT
-
DQ-IN
DQ-IN
Hi-Z
STATE
Standby
Refresh
Byte Read
Byte Read
Word Read
Byte Write
Byte Write
Word Write
-

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관련 데이터시트

부품번호상세설명 및 기능제조사
KM416C1200AT-6T

C-MOS 1M 16-BIT DYNAMIC RAM

ETC
ETC
KM416C1200B

1M x 16Bit CMOS Dynamic RAM with Fast Page Mode

Samsung semiconductor
Samsung semiconductor

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