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부품번호 ISL9N312AD3 기능
기능 N-Channel Logic Level PWM Optimized UltraFET Trench Power MOSFETs
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ISL9N312AD3 데이터시트, 핀배열, 회로
June 2002
ISL9N312AD3 / ISL9N312AD3ST
N-Channel Logic Level PWM Optimized UltraFET® Trench Power MOSFETs
General Description
This device employs a new advanced trench MOSFET
technology and features low gate charge while maintaining
low on-resistance.
Optimized for switching applications, this device improves
the overall efficiency of DC/DC converters and allows
operation to higher switching frequencies.
Applications
• DC/DC converters
Features
• Fast switching
• rDS(ON) = 0.010(Typ), VGS = 10V
• rDS(ON) = 0.017(Typ), VGS = 4.5V
• Qg (Typ) = 13nC, VGS = 5V
• Qgd (Typ) = 4.5nC
• CISS (Typ) = 1450pF
D
G
S
DTO-P-2A5K2
(TO-252)
GDS
I-PAK
(TO-251AA)
D
G
S
MOSFET Maximum Ratings TA = 25°C unless otherwise noted
Symbol
VDSS
VGS
ID
Parameter
Drain to Source Voltage
Gate to Source Voltage
Drain Current
Continuous (TC = 25oC, VGS = 10V)
Continuous (TC = 100oC, VGS = 4.5V)
Continuous (TC = 25oC, VGS = 10V, RθJA = 52oC/W)
Pulsed
PD
Power dissipation
Derate above 25oC
TJ, TSTG Operating and Storage Temperature
Thermal Characteristics
RθJC
RθJA
RθJA
Thermal Resistance Junction to Case TO-251, TO-252
Thermal Resistance Junction to Ambient TO-251, TO-252
Thermal Resistance Junction to Ambient TO-252, 1in2 copper pad area
Package Marking and Ordering Information
Device Marking
N312AD
N312AD
Device
ISL9N312AD3ST
ISL9N312AD3
Package
TO-252AA
TO-251AA
Reel Size
330mm
Tube
Ratings
30
±20
50
32
11
Figure 4
75
0.5
-55 to 175
2
100
52
Units
V
V
A
A
A
A
W
W/oC
oC
oC/W
oC/W
oC/W
Tape Width
16mm
NA
Quantity
2500 units
50 units
©2002 Fairchild Semiconductor Corporation
ISL9N312AD3 / ISL9N312AD3ST Rev C




ISL9N312AD3 pdf, 반도체, 판매, 대치품
Typical Characteristic (Continued) TC = 25°C unless otherwise noted
100
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD = 15V
75
TJ = -55oC
50
TJ = 175oC
TJ = 25oC
25
0
12345
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 5. Transfer Characteristics
6
100
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
TC = 25oC
75
VGS = 10V
VGS = 4.5V
50
VGS = 4V
25
VGS = 3V
0
0 0.5 1.0 1.5
VDS, DRAIN TO SOURCE VOLTAGE (V)
Figure 6. Saturation Characteristics
2.0
25
ID = 14A
20
ID = 32A
ID = 50A
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
15
10
5
2 4 6 8 10
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 7. Drain to Source On Resistance vs Gate
Voltage and Drain Current
2.0
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
1.5
1.0
0.5
-80
VGS = 10V, ID = 50A
-40 0 40 80 120 160 200
TJ, JUNCTION TEMPERATURE (oC)
Figure 8. Normalized Drain to Source On
Resistance vs Junction Temperature
1.2 1.2
VGS = VDS, ID = 250µA
ID = 250µA
1.0
1.1
0.8
1.0
0.6
0.4
-80
-40 0 40 80 120 160
TJ, JUNCTION TEMPERATURE (oC)
200
Figure 9. Normalized Gate Threshold Voltage vs
Junction Temperature
0.9
-80 -40 0 40 80 120 160 200
TJ, JUNCTION TEMPERATURE (oC)
Figure 10. Normalized Drain to Source
Breakdown Voltage vs Junction Temperature
©2002 Fairchild Semiconductor Corporation
ISL9N312AD3 / ISL9N312AD3ST Rev C

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ISL9N312AD3 전자부품, 판매, 대치품
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, TJM, and the
thermal resistance of the heat dissipating path determines
the maximum allowable device power dissipation, PDM, in an
application.
Therefore the applications ambient
temperature, TA (oC), and thermal resistance RθJA (oC/W)
must be reviewed to ensure that TJM is never exceeded.
Equation 1 mathematically represents the relationship and
serves as the basis for establishing the rating of the part.
125
100
75
PDM
=
-(--T----J---M------–-----T---A-----)
ZθJA
(EQ. 1)
50
RθJA = 33.32 + 23.84/(0.268+Area)
In using surface mount devices such as the TO-252
package, the environment in which it is applied will have a
significant influence on the parts current and maximum
power dissipation ratings. Precise determination of PDM is
complex and influenced by many factors:
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.
2. The number of copper layers and the thickness of the
board.
3. The use of external heat sinks.
4. The use of thermal vias.
5. Air flow and board orientation.
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
Fairchild provides thermal information to assist the
designers preliminary application evaluation. Figure 21
defines the RθJA for the device as a function of the top
copper (component side) area. This is for a horizontally
positioned FR-4 board with 1oz copper after 1000 seconds
of steady state power with no air flow. This graph provides
the necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse
applications can be evaluated using the Fairchild device
Spice thermal model or manually utilizing the normalized
maximum transient thermal impedance curve.
Displayed on the curve are RθJA values listed in the
Electrical Specifications table. The points were chosen to
depict the compromise between the copper board area, the
thermal resistance and ultimately the power dissipation,
PDM.
Thermal resistances corresponding to other copper areas
can be obtained from Figure 21 or by calculation using
Equation 2. RθJA is defined as the natural log of the area
times a coefficient added to a constant. The area, in square
inches is the top copper area including the gate and source
pads.
RθJA
=
33.32 +
------------2---3---.--8---4-------------
(0.268 + Area)
(EQ. 2)
25
0.01
0.1
1
10
AREA, TOP COPPER AREA (in2)
Figure 21. Thermal Resistance vs Mounting
Pad Area
©2002 Fairchild Semiconductor Corporation
ISL9N312AD3 / ISL9N312AD3ST Rev C

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부품번호상세설명 및 기능제조사
ISL9N312AD3

N-Channel Logic Level PWM Optimized UltraFET Trench Power MOSFETs

Fairchild Semiconductor
Fairchild Semiconductor
ISL9N312AD3ST

N-Channel Logic Level PWM Optimized UltraFET Trench Power MOSFETs

Fairchild Semiconductor
Fairchild Semiconductor

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