PDF ISPMACH4ACPLDFAMILY Data sheet ( Hoja de datos )

Número de pieza	ISPMACH4ACPLDFAMILY
Descripción	High Performance E 2 CMOS In-System Programmable Logic
Fabricantes	Lattice Semiconductor
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No Preview Available ! ispMACH™ 4A CPLD Family High Performance E2CMOS® In-System Programmable Logic FEATURES x High-performance, E2CMOS 3.3-V & 5-V CPLD families x Flexible architecture for rapid logic designs — Excellent First-Time-FitTM and reﬁt feature — SpeedLockingTM performance for guaranteed ﬁxed timing — Central, input and output switch matrices for 100% routability and 100% pin-out retention x High speed — 5.0ns tPD Commercial and 7.5ns tPD Industrial — 182MHz fCNT x 32 to 512 macrocells; 32 to 768 registers x 44 to 388 pins in PLCC, PQFP, TQFP, BGA, fpBGA and caBGA packages x Flexible architecture for a wide range of design styles — D/T registers and latches — Synchronous or asynchronous mode — Dedicated input registers — Programmable polarity — Reset/ preset swapping x Advanced capabilities for easy system integration — 3.3-V & 5-V JEDEC-compliant operations — JTAG (IEEE 1149.1) compliant for boundary scan testing — 3.3-V & 5-V JTAG in-system programming — PCI compliant (-5/-55/-6/-65/-7/-10/-12 speed grades) — Safe for mixed supply voltage system designs — Programmable pull-up or Bus-FriendlyTM inputs and I/Os — Hot-socketing — Programmable security bit — Individual output slew rate control x Advanced E2CMOS process provides high-performance, cost-effective solutions x Supported by ispDesignEXPERTTM software for rapid logic development — Supports HDL design methodologies with results optimized for ispMACH 4A — Flexibility to adapt to user requirements — Software partnerships that ensure customer success x Lattice and third-party hardware programming support — LatticePROTM software for in-system programmability support on PCs and automated test equipment — Programming support on all major programmers including Data I/O, BP Microsystems, Advin, and System General Publication# ISPM4A Rev: D Amendment/0 Issue Date: August 2000 1 page FUNCTIONAL DESCRIPTION The fundamental architecture of ispMACH 4A devices (Figure 1) consists of multiple, optimized PAL® blocks interconnected by a central switch matrix. The central switch matrix allows communication between PAL blocks and routes inputs to the PAL blocks. Together, the PAL blocks and central switch matrix allow the logic designer to create large designs in a single device instead of having to use multiple devices. The key to being able to make effective use of these devices lies in the interconnect schemes. In the ispMACH 4A architecture, the macrocells are ﬂexibly coupled to the product terms through the logic allocator, and the I/O pins are ﬂexibly coupled to the macrocells due to the output switch matrix. In addition, more input routing options are provided by the input switch matrix. These resources provide the ﬂexibility needed to ﬁt designs efﬁciently. Clock/Input Pins Note 3 Dedicated Input Pins Clock Generator 4 Note 2 PAL Block 33/ 34/ 36 Logic Array Input Switch Matrix Logic 16 Output/ 16 Allocator Buried with XOR Macrocells 16 PAL Block 8 Note 1 16 I/O Pins I/O Pins PAL Block Figure 1. ispMACH 4A Block Diagram and PAL Block Structure I/O Pins 17466G-001 Notes: 1. 16 for ispMACH 4A devices with 1:1 macrocell-I/O cell ratio (see next page). 2. Block clocks do not go to I/O cells in M4A(3,5)-32/32. 3. M4A(3,5)-192, M4A(3,5)-256, M4A3-384, and M4A3-512 have dedicated clock pins which cannot be used as inputs and do not connect to the central switch matrix. ispMACH 4A Family 5 5 Page The ﬂip-ﬂop can be conﬁgured as a D-type or T-type latch. J-K or S-R registers can be synthesized. The primary ﬂip-ﬂop conﬁgurations are shown in Figure 6, although others are possible. Flip-ﬂop functionality is deﬁned in Table 8. Note that a J-K latch is inadvisable as it will cause oscillation if both J and K inputs are HIGH. AP AR DQ AP AR DQ a. D-type with XOR AP AR LQ G c. Latch with XOR AP AR TQ e. T-type with programmable T polarity b. D-type with programmable D polarity AP AR LQ G d. Latch with programmable D polarity f. Combinatorial with XOR g. Combinatorial with programmable polarity Figure 6. Primary Macrocell Conﬁgurations ispMACH 4A Family 17466G-011 11 11 Page

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