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ispPAC10-01SI 데이터시트 PDF




Lattice Semiconductor에서 제조한 전자 부품 ispPAC10-01SI은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

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부품번호 ispPAC10-01SI 기능
기능 In-System Programmable Analog Circuit
제조업체 Lattice Semiconductor
로고 Lattice Semiconductor 로고


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ispPAC10-01SI 데이터시트, 핀배열, 회로
ispPAC ®10
In-System Programmable Analog Circuit
Features
• IN-SYSTEM PROGRAMMABLE (ISP™) ANALOG CIRCUIT
— Four Instrument Amplifier Gain/Attenuation Stages
— Signal Summation (Up to 4 Inputs)
— Precision Active Filtering (10kHz to 100kHz)
— No External Components Needed for Configuration
— Non-Volatile E2CMOS® Cells (10,000 Cycles)
— IEEE 1149.1 JTAG Serial Port Programming
• FOUR LINEAR ELEMENT BUILDING BLOCKS
— Programmable Gain Range (0dB to 80dB)
— Bandwidth of 550kHz (G=1), 330kHz (G=10)
— Low Distortion (THD < -74dB max @ 10kHz)
— Auto-Calibrated Input Offset Voltage
• TRUE DIFFERENTIAL I/O (±3V RANGE)
— High CMR (69dB) Instrument Amplifier Inputs
— 2.5V Common Mode Reference on Chip
— Four Rail-to-Rail Voltage Outputs
• 28-PIN PLASTIC DIP OR SOIC PACKAGE
— Single Supply 5V Operation
• APPLICATIONS INCLUDE INTEGRATED:
— Single +5V Supply Signal Conditioning
— Active Filters, Gain Stages, Summing Blocks
— Analog Front Ends, 12-Bit Data Acq. Systems
— Sensor Signal Conditioning
Description
Functional Block Diagram
OUT2+ 1
OUT22
IN2+ 3
IN24
TDI 5
TRST 6
VS 7
TDO 8
TCK 9
TMS 10
IN411
IN4+ 12
OUT413
OUT4+ 14
OA OA
IA IA
IA IA
Configuration Memory
Analog Routing Pool
Reference & Auto-Calibration
IA IA
IA IA
OA OA
28 OUT1+
27 OUT1
26 IN1+
25 IN1
24 TEST
23 TEST
22 VREFOUT
21 GND
20 CAL
19 CMVIN
18 IN3
17 IN3+
16 OUT3
15 OUT3+
The ispPAC10 is a member of the Lattice family of In-
System Programmable analog circuits, digitally configured
via nonvolatile E2CMOS technology.
Typical Application Diagram
Analog function modules, called PACblocks™, replace
traditional analog components such as op amps and
active filters, eliminating the need for most external
resistors and capacitors. With no requirement for exter-
nal configuration components, ispPAC10 expedites the
design process, simplifying prototype circuit implemen-
tation and change, while providing high performance and
integrated functionality.
Vin
5V
5V
12-Bit
Differential
Input ADC
Ain+
Ain-
Designers configure the ispPAC10 and verify its perfor-
mance using PAC-Designer®, an easy-to-use, Microsoft
Windows® compatible development tool. Device pro-
gramming is supported using PC parallel port I/O
operations. A library of configurations is included with basic
solutions and examples of advanced circuit techniques.
Ref+
The ispPAC10 is configured through its IEEE Standard
1149.1 (JTAG) compliant serial port. The flexible In-
System Programming capability enables programming,
verification and reconfiguration if desired, directly on the
printed circuit board.
ispPAC10
Ref-
Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
September 2000
pac10_04
1




ispPAC10-01SI pdf, 반도체, 판매, 대치품
Specifications ispPAC10
Timing Specifications
TA = 25°C; VS = +5.0V (Unless otherwise specified).
SYMBOL
PARAMETER
CONDITION
Dynamic Performance
tckmin Minimum Clock Period
tckh TCK High Time
tckl TCK Low Time
tmss
TMS Setup Time
tmsh
TMS Hold Time
tdis TDI Setup Time
tdih TDI Hold Time
tdozx TDO Float to Valid Delay
tdov TDO Valid Delay
tdoxz TDO Valid to Float Delay
trstmin Minimum reset pulse width
tpwp
Time for a programming operation
tpwe
Time for an erase operation
tpwcal1 Time for auto-cal operation on power-up
tcalmin Minimum auto-cal pulse width
tpwcal2 Time for user initiated auto-cal operation
Executed in Run-Test/Idle
Executed in Run-Test/Idle
Automatically executed at power-up
Executed on rising edge of CAL
MIN.
200
50
50
15
10
15
10
40
80
80
40
TYP.
MAX. UNITS
ns
ns
ns
ns
ns
ns
ns
60 ns
60 ns
60 ns
ns
100 ms
100 ms
250 ms
ns
100 ms
tckh tckl
tckmin
tpwp, tpwe
TCK
tmss tmsh
TMS
tdis tdih
TCK
tmss
tmss
TMS
*(PRGUSR/UBE executed in
Run-Test/Idle state)
TDI
TDO
tdozx
tdov
tdoxz
CAL
VOUT
(Note: CAL internally
initiated at device turn-on.)
tcalmin
VOUT = 0VDIFF
tpwcal1, tpwcal2
*Note: During device JTAG programming, analog outputs will stop responding to normal input stimulus. This is because all
configuration information is erased and then re-written as part of a normal programming cycle, momentarily disrupting the input
to output signal path. Behavior is not predictable during either of these steps since the analog outputs are not clamped during
a programming cycle. Usually, however, the outputs will slew to either 0V (Ground) or 5V (Vsupply) or 2.5V (VREFOUT). This
behavior is partially determined by conditions existing immediately prior to device reprogramming and intermediate configura-
tions that occur during the process.
4

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ispPAC10-01SI 전자부품, 판매, 대치품
Specifications ispPAC10
Typical Performance Characteristics
10.34kHz Filter FC Accuracy
50
2000 Units
PDIP Pkg
40
46.46kHz Filter F Accuracy
C
50
2000 Units
PDIP Pkg
40
91.98kHz Filter FC Accuracy
50
2000 Units
PDIP Pkg
40
30 30 30
20 20 20
10
0
-4 -3 -2 -1 0 1 2 3 4
Frequency Variation (%)
Large-Signal Response
10 10
0
-4 -3 -2 -1 0 1 2 3 4
Frequency Variation (%)
0
-4 -3 -2 -1 0 1 2 3 4
Frequency Variation (%)
Small-Signal Response
1.0V
1µS
Gain = 1
Load = No Load
Large-Signal Response with 600pF Load
20mV
1µS
Gain = 1
Load = No Load
Small-Signal Response with 600pF Load
1.0V
Gain = 1
Load = 600pF
1µS
20mV
Gain = 1
Load = 600pF
7
1µS

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부품번호상세설명 및 기능제조사
ispPAC10-01SI

In-System Programmable Analog Circuit

Lattice Semiconductor
Lattice Semiconductor

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