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부품번호 | IW4013BN 기능 |
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기능 | Dual D Flip-Flop High-Voltage Silicon-Gate CMOS | ||
제조업체 | ETC | ||
로고 | |||
TECHNICAL DATA
Dual D Flip-Flop
High-Voltage Silicon-Gate CMOS
IW4013B
The IW4013B consists of two identical, independent data-type flip-
flops. Each flip-flop has independent data, set, reset, and clock inputs
and Q and Q outputs. These devices can be used for shift register
applications, and, by connecting Q output to the data input, for counter
and toggle applications. The logic level present at the D input is
transferred to the Q output during the positive-going transition of the
clock pulse. Setting or resetting is independent of the clock and is
accomplished by a high level on the set or reset line, respectively.
• Operating Voltage Range: 3.0 to 18 V
• Maximum input current of 1 µA at 18 V over full package-
temperature range; 100 nA at 18 V and 25°C
• Noise margin (over full package temperature range):
1.0 V min @ 5.0 V supply
2.0 V min @ 10.0 V supply
2.5 V min @ 15.0 V supply
ORDERING INFORMATION
IW4013BN Plastic
IW4013BD SOIC
TA = -55° to 125° C for all packages
LOGIC DIAGRAM
PIN ASSIGNMENT
PIN 14 =VCC
PIN 7 = GND
FUNCTION TABLE
Inputs
Clock Data Reset Set
L LL
H LL
X LL
X X HL
X X LH
X X HH
Outputs
QQ
LH
HL
QQ
LH
HL
HH
X = don’t care
19
IW4013B
AC ELECTRICAL CHARACTERISTICS(CL=50pF, RL=200 kΩ, Input tr=tf=20 ns)
Symbol
Parameter
VCC Guaranteed Limit
V ≥-55°C 25°C ≤125°C Unit
fmax Maximum Clock Frequency (Figure 1)
5.0 3.5
10 8
15 12
3.5 1.75 MHz
84
12 6
tPLH, tPHL Maximum Propagation Delay, Clock to Q or Q 5.0 300 300 600 ns
(Figure 1)
10 130 130 260
15 90
90 180
tPLH Maximum Propagation Delay, Set to Q or Reset 5.0 300 300 600 ns
to Q (Figure 2)
10 130 130 260
15 90
90 180
tPHL Maximum Propagation Delay, Set to Q or Reset 5.0 400 400 800 ns
to Q (Figure 2)
10 170 170 340
15 120 120 240
tTLH, tTHL Maximum Output Transition Time, Any Output 5.0 200 200 400 ns
(Figure 1)
10 100 100 200
15 80
80 160
CIN Maximum Input Capacitance
- 7.5 pF
TIMING REQUIREMENTS(CL=50pF, RL=200 kΩ, Input tr=tf=20 ns)
Symbol
Parameter
tw Minimum Pulse Width, Clock (Figure 1)
tw Minimum Pulse Width, Set or Reset (Figure 2)
tsu Minimum Setup Time, Data to Clock
(Figure 3)
th Minimum Hold Time, Clock to Data
(Figure 3)
tr, tf Maximum Input Rise or Fall Time, Clock
(Figure 1)
VCC Guaranteed Limit
V ≥-55°C 25°C ≤125°C
5.0 140 140 280
10 60
60 120
15 40 40 80
5.0 180 180 360
10 80
80 160
15 50
50 100
5.0 40 40 80
10 20 20 40
15 15 15 30
5.0 5
10 5
15 5
5 10
5 10
5 10
5.0 500
10 30
15 6
500 1000
30 60
6 12
Unit
ns
ns
ns
ns
µs
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다운로드 | [ IW4013BN.PDF 데이터시트 ] |
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구매 문의 | 일반 IC 문의 : 샘플 및 소량 구매 ----------------------------------------------------------------------- IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한 광범위한 전력 반도체를 판매합니다. 전력 반도체 전문업체 상호 : 아이지 인터내셔날 사이트 방문 : [ 홈페이지 ] [ 블로그 1 ] [ 블로그 2 ] |
부품번호 | 상세설명 및 기능 | 제조사 |
IW4013B | Dual D Flip-Flop High-Voltage Silicon-Gate CMOS | ETC |
IW4013B | Dual D-Type Flip-Flop | IK Semiconductor |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |