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PDF IMP811 Data sheet ( Hoja de datos )
| Número de pieza | IMP811 | |
| Descripción | POWER MANAGEMENT | |
| Fabricantes | IMP Inc | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de IMP811 (archivo pdf) en la parte inferior de esta página. Total 9 Páginas | ||
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ISO 9001 Registered
IMP811, IMP812
POWER MANAGEMENT
General Description
Key Features
The IMP811/IMP812 are low-power supervisors
designed to monitor voltage levels of 2.5V,3.0V,
3.3V and 5.0V power supplies in low-power micro-
processor (µP), microcontroller (µC) and digital
systems. Each fea-tures a debounced manual reset
input. The IMP811/812 are improved drop-in re-
placements for the Maxim MAX811/812 with ex-
tended temperature specifications to 125°C.
A reset signal is issued if the power supply voltage
drops below a preset threshold and is asserted for at
least 140ms after the supply has risen above the reset
threshold. The IMP811 has an active-low output
RESET that is guaranteed to be in the correct state
for VCC down to 1.1V. The IMP812 has an active-
high output RESET. The reset comparator is de-
signed to ignore fast transients on VCC.
Low power consumption makes the IMP811/
IMP812 ideal for use in portable and battery-
operated equipment. Available in a compact 4-pin
SOT143 package, the devices use minimal board
space.
Three voltage thresholds are available to support
2.5V to 5V systems:
• Improved Maxim MAX811/MAX812
replacement
—Specified to 125°C
• 6µA supply current
• Monitor 5V,3.3V,3V and 2.5V supplies
• Manual reset input
• 140ms min. reset pulse width
• Guaranteed over temperature
• Active-LOW reset valid with 1.1V supply
(IMP811)
• Small 4-pin SOT-143 package
• No external components
• Power-supply transient-immune design
Applications
- Computers and controllers
- Embedded controllers
- Battery operated systems
- Intelligent instruments
- Wireless communication systems
- PDAs and handheld equipment
Block Diagram
Reset Threshold
Suffix
Voltage (V)
L 4.63
M 4.38
J 4.00
T 3.08
S 2.93
R 2.63
Z 2.32
VCC
VCC
IMP811
(IMP812)
¯R¯E¯S¯E¯¯T
¯M¯R¯ RESET
VCC
¯R¯E¯S¯E¯T¯
Input
GND
GND
Daily Silver IMP
www.ds-imp.com.cn
1
1 page  
ISO 9001 Registered
IMP811, IMP812
POWER MANAGEMENT
Typical Performance Characteristics
Reset Timing and Manual Reset (M¯¯R¯ )
The reset signal is asserted–LOW for the IMP811 and HIGH for the IMP812 – when the VCC signal falls
below the threshold trip voltage and remains asserted for 140ms minimum after the VCC has risen above
the threshold.
Alogic low on ¯M¯R¯ asserts RESET LOW on the IMP811 and HIGH on the IMP812.¯M¯¯R is internally pulled
high through a 20kΩ resistor and can be driven by TTL/CMOS gates or with open collector/drain outputs.
M¯¯R¯ can be left open if not used.
¯M¯¯R may be connected to a normally-open switch connected to ground without an external debounce circuit.
For added noise rejection, a 0.1μF capacitor from ¯M¯R¯ to Ground can be added.
5V
VCC
0V
¯M¯R¯ 5V
0V
R¯¯E¯S¯E¯T¯ 5V
0V
5V
RESET
0V
Active Reset
Timeout Period
VTH
Active Reset
Timeout Period
140ms
minimum
IMP811
IMP812
Figure 1. Reset Timing Diagram
RESET Output Operation
In μP/μC systems it is important to have the processor begin operation from a known state or be able to
return the system to a known state. A RESET output to a processor is provided to prevent improper op-
eration during power supply sequencing or low voltage – brownout – conditions.
The IMP811/812 are designed to monitor the system power supply voltages and issue a RESET signal
when levels are out of range. RESET outputs are guaranteed to be active for VCC above 1.1V. When VCC
exceeds the reset threshold, an internal timer keeps RESET active for the reset timeout period, after which
RESET becomes inactive (HIGH for the IMP811 and LOW for the IMP812).
Daily Silver IMP
www.ds-imp.com.cn
5
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet IMP811.PDF ] | |
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