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부품번호 | IMSA110 기능 |
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기능 | IMAGE AND SIGNAL PROCESSING SUB.SYSTEM | ||
제조업체 | STMicroelectronics | ||
로고 | |||
전체 26 페이지수
IMSA110
IMAGE AND SIGNAL PROCESSING SUB–SYSTEM
. 1-D/2-D SOFTWARE CONFIGURABLE CON-
VOLVER/FILTER
. ON-CHIP PROGRAMMABLE LINE DELAYS (0
— 1120 STAGES)
. 8-BIT DATA AND 8.5-BIT COEFFICIENT
SLICE
. 21 MULTIPLY-AND-ACCUMULATE STAGES
. 1-D (21) OR 2-D (3 x 7) CONVOLUTION WIN-
DOW
. ON-CHIP POST PROCESSOR FOR DATA
TRANSFORMATION
. FULLY CASCADABLE IN WINDOW SIZE AND
ACCURACY
. 20 MHZ DATA THROUGHPUT (420 MOPS)
. SIGNED/UNSIGNED DATA AND COEFFI-
CIENTS
. MICROPROCESSOR INTERFACE
. HIGH SPEED CMOS IMPLEMENTATION
. TTL COMPATIBLE
. SINGLE +5V ± 10% SUPPLY
. POWER DISSIPATION < 2.0 WATTS
. 100 PIN CERAMIC PGA
PGA100
(Ceramic Grid Array Package)
APPLICATIONS
. 1-D and 2-D digital convolution and correlation
. Real time image processing and enhancement
. Edge and feature detection
. Data transformation and histogram equalisa-
tion
. Computer vision and robotics
. Template matching
. Pulse compression
. 1-D or 2-D interpolation
ORDERING INFORMATION
Part Number
Package
Clock
Speed
IMSA110-G20S PGA100 20MHz
Military/
commercial
commercial
July 1992
1/26
IMSA110
Figure 2 : Synchronous Functions of the IMSA110
PSRIN
1D
8
Programmable PSRC
shift register
0 to 1120 stages
D
1
D
1
2
8
CR1c coefficient registers 7 x 8 bits
CR0c coefficient registers 7 x 8 bits
D
3
X
X
1
D
XX
1 11
D DD
22
D
Programmable PSRB
shift register
0 to 1120 stages
D
1
D
1
2
8
CR1b coefficient registers 7 x 8 bits
CR0b coefficient registers 7 x 8 bits
D
3
X
X
1
D
XX
1 11
D DD
22
D
Programmable PSRA
shift register
0 to 1120 stages
D
1
D
1
2
D
3
MUX
1D
8
PSROUT
1
2
D
CIN
cascade input
CR1a coefficient registers 7 x 8 bits
CR0a coefficient registers 7 x 8 bits
X
1
D
X
X
11
DD
22
D
13
Backend processing unit
including cascade data path,
normalization, saturation units and
data transformation look up tables
(see Figure 4 for detail)
X
1
D
22
D
5
1
2
COUT
cascade output
4/26
4페이지 IMSA110
Figure 4 : Detailed Block Diagram of the Backend Post-processing Unit
Clock
cycle
1
2
3
Cascade input pads
22
MUX
22
negative overflow
positive overflow
1
1
DATA TRANSFORMATION
UNIT
Prescaler
Over/under select
(Isbs) 2
8
6
USR
LSR
22
64 x 32 bit RAM
Cascade Adder
22
22
Shifter [8:0]
From MAC array
22
1
Rounding
Rectifier
22
STATISTICS MONITOR
Min/max buffer
22
Min/max register
22
Comparator GT/LT
Over/undershoot count
22
Over/undershoot buffer
Control
32 Y bus
[26:22] 5
DATA NORMALIZER
[21:0]
32
Shifter -2 to 14
Zero data
4
Byte select
from
BCR
8
22 MUX
1
22
Rounding
22
Output Adder
22
5
[21:14] 8
8 [7:0]
6
MUX
[13:8]
MUX
88
[21:14]
[7:0]
6
22
Cascade output pads
7/26
7페이지 | |||
구 성 | 총 26 페이지수 | ||
다운로드 | [ IMSA110.PDF 데이터시트 ] |
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구매 문의 | 일반 IC 문의 : 샘플 및 소량 구매 ----------------------------------------------------------------------- IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한 광범위한 전력 반도체를 판매합니다. 전력 반도체 전문업체 상호 : 아이지 인터내셔날 사이트 방문 : [ 홈페이지 ] [ 블로그 1 ] [ 블로그 2 ] |
부품번호 | 상세설명 및 기능 | 제조사 |
IMSA110 | IMAGE AND SIGNAL PROCESSING SUB.SYSTEM | STMicroelectronics |
IMSA110-G20S | IMAGE AND SIGNAL PROCESSING SUB.SYSTEM | STMicroelectronics |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |