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PDF IMSC011-W20S Data sheet ( Hoja de datos )
| Número de pieza | IMSC011-W20S | |
| Descripción | Link adaptor | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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FEATURES
H Standard INMOS link protocol
H 10 or 20 Mbits/sec operating speed
H Communicates with transputers
H Converts between serial link and parallel bus
H Converts between serial link and parallel device
H Two modes of parallel operation:
Mode 1: Peripheral interface
Eight bit parallel input interface
Eight bit parallel output interface
Full handshake on input and output
Mode 2: Bus interface
Tristate bidirectional bus interface
Memory mapped registers
Interrupt capability
H Single +5V 5% power supply
H TTL and CMOS compatibility
H 120mW power dissipation
H 28 pin 0.6” plastic package
H 28 pin SOJ package
H 28 pin LCCC package
H Extended temperature version available
APPLICATIONS
H Programmable I/O for transputer
H Connecting microprocessors to transputers
H High speed links between microprocessors
H Inter-family microprocessor interfacing
H Interconnecting different speed links
IMS C011
Link adaptor
System
Services
Input
Interface
8
Output
8
Link Interface
Mode 1
System
Services
Interrupt
Control
Register
Select
Data and
Link
Status
8
Registers
Mode 2
July 1995
42 1412 08
1/30
1 page  
3 System services
3 System services
System services include all the necessary logic to start up and maintain the IMS C011.
3.1 Power
Power is supplied to the device via the VDD and GND pins. The supply must be decoupled close to the
chip by at least one 100 nF low inductance (e.g. ceramic) capacitor between VDD and GND. Four layer
boards are recommended; if two layer boards are used, extra care should be taken in decoupling.
AC noise between VDD and GND must be kept below 200 mV peak to peak at all frequencies above
100 KHz. AC noise between VDD and the ground reference of load capacitances must be kept below
200 mV peak to peak at all frequencies above 30 MHz. Input voltages must not exceed specification with
respect to VDD and GND, even during power-up and power-down ramping, otherwise latchup can occur.
CMOS devices can be permanently damaged by excessive periods of latchup.
3.2 CapMinus
The internally derived power supply for internal clocks requires an external low leakage, low inductance
1mF capacitor to be connected between VDD and CapMinus. A ceramic capacitor is preferred, with an
impedance less than 3 Ohms between 100 KHz and 10 MHz. If a polarised capacitor is used the negative
terminal should be connected to CapMinus. Total PCB track length should be less than 50 mm. The posi-
tive connection of the capacitor must be connected directly to VDD. Connections must not otherwise touch
power supplies or other noise sources.
Phase–locked
loops
GND
VDD
VDD pin P.C.B track
Decoupling
capacitor 1 mF
CapMinus P.C.B track
Figure 3.1 Recommended PLL decoupling
3.3 ClockIn
Transputer family components use a standard clock frequency, supplied by the user on the ClockIn input.
The nominal frequency of this clock for all transputer family components is 5 MHz, regardless of device
type, transputer word length or processor cycle time. High frequency internal clocks are derived from
ClockIn, simplifying system design and avoiding problems of distributing high speed clocks externally.
A number of transputer family devices may be connected to a common clock, or may have individual clocks
providing each one meets the specified stability criteria. In a multi-clock system the relative phasing of
ClockIn clocks is not important, due to the asynchronous nature of the links. Mark/space ratio is unimpor-
tant provided the specified limits of ClockIn pulse widths are met.
Oscillator stability is important. ClockIn must be derived from a crystal oscillator; RC oscillators are not
sufficiently stable. ClockIn must not be distributed through a long chain of buffers. Clock edges must be
monotonic and remain within the specified voltage and time limits.
5 / 30
5 Page 
4 Links
Transputer family device A
LinkOut
LinkIn
LinkIn
LinkOut
Transputer family device B
Figure 4.4 Links directly connected
Transputer family device A
LinkOut
RM
Zo=100 ohms
LinkIn
Zo=100 ohms
RM
LinkIn
LinkOut
Transputer family device B
Figure 4.5 Links connected by transmission line
Transputer family device A
LinkOut
LinkIn
buffers
LinkIn
LinkOut
Transputer family device B
Figure 4.6 Links connected by buffers
11 / 30
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet IMSC011-W20S.PDF ] | |
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