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PDF IP1843 Data sheet ( Hoja de datos )
| Número de pieza | IP1843 | |
| Descripción | CURRENT MODE REGULATING PULSE WIDTH MODULATORS | |
| Fabricantes | Seme LAB | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de IP1843 (archivo pdf) en la parte inferior de esta página. Total 6 Páginas | ||
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IP1842 SERIES
IP1843 SERIES
TOP VIEW
COMP 1
VFB 2
ISENSE 3
RT /CT 4
8 VREF
7 VCC
6 OUTPUT
5 GROUND
CURRENT MODE
REGULATING
PULSE WIDTH
MODULATORS
J Package – 8 Pin Ceramic DIP
N Package – 8 Pin Plastic DIP
D-8 Package – 8 Pin Plastic (150) SOIC
TOP VIEW
COMP 1
N/C 2
VFB 3
N/C 4
ISENSE 5
N/C 6
RT /CT 7
14 VREF
13 N/C
12 VCC
11 VC
10 OUTPUT
9 GROUND
POWER
8 GROUND
FEATURES
• Guaranteed ±1% reference voltage tolerance
• Guaranteed ±10% frequency tolerance
• Low start–up current (<500 mA)
• Under voltage lockout with hysteresis
• Output state completely defined for all supply
and input conditions
• Interchangeable with UC1842 and UC1843
series for improved operation
• 500kHz operation
D-14 Package – 14 Pin Plastic (150) SOIC
Order Information
Part
Number
IP1842
IP2842
IP3842
IP1843
IP2843
IP3843
J–Pack
8 Pin
✔
✔
✔
✔
✔
✔
N–Pack
8 Pin
✔
✔
✔
✔
D–8
8 Pin
✔
✔
✔
✔
D–14
14 Pin
✔
✔
✔
✔
Temp.
Range
-55 to +125°C
-25 to +85°C
0 to +70°C
-55 to +125°C
-25 to +85°C
0 to +70°C
Note:
To order, add the package identifier to the
part number.
eg. IP1842J
IP3843D-14
ABSOLUTE MAXIMUM RATINGS (Tcase = 25°C unless otherwise stated)
VCC Supply Voltage
IO Output Current
Output Energy
(low impedance source)
(ICC < 30mA)
(capacitive load)
+30V
Self limiting
±1A
5mJ
Analog Inputs
(pins 2 and 3)
Error Amp Output Sink Current
–0.3V to +VCC
10mA
PD
PD
TSTG
TL
Power Dissipation
Derate @ Tamb > 50°C
Power Dissipation
Derate @ Tcase > 25°C
Storage Temperature Range
Lead Temperature
Tamb = 25°C
Tcase = 25°C
(soldering, 10 seconds)
1W
10mW/°C
2W
24mW/°C
–65 to 150°C
+300°C
Semelab plc. Telephone +44(0)1455 556565. Fax +44(0)1455 552612.
Prelim.3/00
1 page  
IP1842 SERIES
IP1843 SERIES
APPLICATIONS INFORMATION
Oscillator Waveforms and Maximum Duty Cycle
COMP 1
VFB 2
ISENSE 3
RT /CT 4
8 VREF
7 VCC
6 OUTPUT
5 GROUND
Oscillator timing capacitor CT is charged by VREF
through RT and discharged by an internal current source.
During the discharge time, the internal clock signal
blanks the output to the low state. Selection of RT and
CT therefore determines both oscillator frequency and
maximum duty cycle. Charge and discharge times are
determined by the formulae:
tc » 0.55 RTCT
( )td » RTCT Rn
.0063 RT – 2.3
.0063 – 4
Resultant frequency
f
=
(tc
1
+
td)
For RT > 5kW,
Resultant frequency
f»
1.8
(RTCT)
Open–Loop Laboratory Test Fixture
COMP 1
N/C 2
VFB 3
N/C 4
ISENSE 5
N/C 6
RT /CT 7
14 VREF
13 N/C
12 VCC
11 VC
10 OUTPUT
9 GROUND
POWER
8 GROUND
High peak current associated with capacitive loads necessitate careful grounding techniques. Timing and bypass capacitors should
be connected close to pin 5 in a single point ground. The transistor and 5K potentiometer are used to sample the oscillator wave
form and apply an adjustable ramp to pin 3.
Semelab plc. Telephone +44(0)1455 556565. Fax +44(0)1455 552612.
Prelim.3/00
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet IP1843.PDF ] | |
Hoja de datos destacado
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