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IDT71421SA35PF 데이터시트 PDF




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부품번호 IDT71421SA35PF 기능
기능 HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS
제조업체 Integrated Device Technology
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IDT71421SA35PF 데이터시트, 핀배열, 회로
Integrated Device Technology, Inc.
HIGH-SPEED 2K x 8
DUAL-PORT STATIC RAM
WITH INTERRUPTS
IDT71321SA/LA
IDT71421SA/LA
FEATURES:
• High-speed access
—Commercial: 20/25/35/45/55ns (max.)
• Low-power operation
—IDT71321/IDT71421SA
—Active: 550mW (typ.)
—Standby: 5mW (typ.)
—IDT71321/421LA
—Active: 550mW (typ.)
—Standby: 1mW (typ.)
• Two INT flags for port-to-port communications
• MASTER IDT71321 easily expands data bus width to 16-
or-more-bits using SLAVE IDT71421
• On-chip port arbitration logic (IDT71321 only)
BUSY output flag on IDT71321; BUSY input on IDT71421
• Fully asynchronous operation from either port
• Battery backup operation —2V data retention (LA Only)
• TTL-compatible, single 5V ±10% power supply
• Available in popular hermetic and plastic packages
• Industrial temperature range (–40°C to +85°C) is avail-
able, tested to military electrical specifications
DESCRIPTION:
The IDT71321/IDT71421 are high-speed 2K x 8 Dual-
Port Static RAMs with internal interrupt logic for interproces-
sor communications. The IDT71321 is designed to be used
as a stand-alone 8-bit Dual-Port RAM or as a "MASTER"
Dual-Port RAM together with the IDT71421 "SLAVE" Dual-
Port in 16-bit-or-more word width systems. Using the IDT
MASTER/SLAVE Dual-Port RAM approach in 16-or-more-
bit memory system applications results in full speed, error-
free operation without the need for additional discrete logic.
Both devices provide two independent ports with sepa-
rate control, address, and I/O pins that permit independent,
asynchronous access for reads or writes to any location in
memory. An automatic power down feature, controlled by
CE, permits the on chip circuitry of each port to enter a very
low standby power mode.
Fabricated using IDT's CMOS high-performance technol-
ogy, these devices typically operate on only 550mW of
power. Low-power (LA) versions offer battery backup data
retention capability, with each Dual-Port typically consum-
ing 200µW from a 2V battery.
The IDT71321/IDT71421 devices are packaged in a 52-
pin PLCC, a 64-pin TQFP, and a 64-pin STQFP.
FUNCTIONAL BLOCK DIAGRAM
OEL
WCEL
R/ L
OER
WCER
R/ R
I/O0L- I/O7L
BUSYL(1,2)
A10L
A0L
NOTES:
1. IDT71321 (MASTER): BUSY
is open drain output and
requires pullup resistor of 270.
IDT71421 (SLAVE): BUSY is input.
2. Open drain output: requires pullup
resistor of 270.
(2)
INTL
I/O
Control
I/O
Control
Address
Decoder
CEL
WOEL
R/ L
11
MEMORY
ARRAY
ARBITRATION
and
INTERRUPT
LOGIC
Address
Decoder
11
CER
WOER
R/ R
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
©1996 Integrated Device Technology, Inc.
For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.
6.03
I/O0R-I/O7R
BUSYR (1,2)
A10R
A0R
(2)
INTR
2691 drw 01
OCTOBER 1996
DSC-2691/6
1




IDT71421SA35PF pdf, 반도체, 판매, 대치품
IDT71321SA/LA AND IDT71421SA/LA
HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS
DATA RETENTION CHARACTERISTICS (LA Version Only)
Symbol
Parameter
Test Conditions
VDR
VCC for Data Retention
ICCDR
tCDR(3)
Data Retention Current
Chip Deselect to Data
VCC = 2.0V, CE > VCC - 0.2V COM'L.
VIN > VCC - 0.2V or VIN0.2V
Retention Time
tR(3) Operation Recovery
Time
NOTES:
1. VCC = 2V, TA = +25°C, and is not production tested.
2. tRC = Read Cycle Time
3. This parameter is guaranteed by device characterization but not production tested.
COMMERCIAL TEMPERATURE RANGE
71321LA/71421LA
Min.
Typ.(1) Max.
2.0 — 0
— 100 1500
0 ——
tRC(2) — —
Unit
V
µA
ns
ns
2691 tbl 07
DATA RETENTION WAVEFORM
DATA RETENTION MODE
VCC
CE
4.5V
tCDR
VIH
VDR 2.0V
VDR
4.5V
tR
VIH
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
2691 drw 04
GND to 3.0V
5ns
1.5V
1.5V
Figures 1, 2, and 3
2691 tbl 08
DATA OUT
775
5V
1250
30pF
DATA OUT
775
100pF for 55 and 100ns versions
5V
1250
5pF
Figure 1. AC Output Test Load
5V
Figure 2. Output Test Load
(for tHZ, tLZ, tWZ, and tOW)
* Including scope and jig.
BUSY or INT
270
30pF
2691 drw 05
100pF for 55 and 100ns versions
Figure 3. BUSY and INT
AC Output Test Load
6.03 4

4페이지










IDT71421SA35PF 전자부품, 판매, 대치품
IDT71321SA/LA AND IDT71421SA/LA
HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF WRITE CYCLE NO. 1, (R/W CONTROLLED TIMING)(1,5,8)
tWC
ADDRESS
OE
CE
R/W
DATA OUT
DATA IN
tAS (6)
(4)
tAW
tWZ (7)
tWP (2)
tDW
tWR(3)
tOW
tDH
TIMING WAVEFORM OF WRITE CYCLE NO. 2, (CE CONTROLLED TIMING)(1,5)
tWC
ADDRESS
CE
R/W
(6)
tAS
tAW
tEW (2)
tDW
tWR(3)
tDH
DATA IN
tHZ (7)
(7)
tHZ
(4)
2691 drw 08
NOTES:
1. R/W or CE must be High during all address transitions.
2691 drw 09
2. A write occurs during the overlap (tEW or tWP) of CE = VIL and R/W= VIL.
3. tWR is measured from the earlier of CE or R/W going High to the end of the write cycle.
4. During this period, the l/O pins are in the output state and input signals must not be applied.
5. If the CE Low transition occurs simultaneously with or after the R/W Low transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal (CE or R/W) is asserted last.
7. This parameter is determined be device characterization, but is not production tested. Transition is measured +/- 500mV from steady state
with the Output Test Load (Figure 2).
8. If OE is Low during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off
data to be placed on the bus for the required tDW. If OE is High during a R/W controlled write cycle, this requirement does not apply and the
write pulse can be as short as the specified tWP.
6.03 7

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IDT71421SA35PF

HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS

Integrated Device Technology
Integrated Device Technology

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