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IDT7198L85LB PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 IDT7198L85LB
기능 CMOS STATIC RAMs 64K (16K x 4-BIT) Added Chip Select and Output Controls
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IDT7198L85LB 데이터시트, 핀배열, 회로
®
Integrated Device Technology, Inc.
CMOS STATIC RAMs
64K (16K x 4-BIT)
Added Chip Select and Output Controls
IDT7198S
IDT7198L
FEATURES:
• Fast Output Enable (OE) pin available for added system
flexibility
• Multiple Chip Selects (CS1, CS2) simplify system design
and operation
• High speed (equal access and cycle times)
— Military: 20/25/35/45/55/70/85ns (max.)
• Low power consumption
• Battery back-up operation—2V data retention (L version
only)
• 24-pin CERDIP, high-density 28-pin leadless chip carrier,
and 24-pin CERPACK packaging available
• Produced with advanced CMOS technology
• Bidirectional data inputs and outputs
• Inputs/outputs TTL-compatible
• Military product compliant to MIL-STD-883, Class B
DESCRIPTION:
The IDT7198 is a 65,536 bit high-speed static RAM orga-
nized as 16K x 4. It is fabricated using IDT’s high-perfor-
mance, high-reliability technology—CMOS. This state-of-the-
art technology, combined with innovative circuit design tech-
niques, provides a cost effective approach for memory inten-
sive applications.
Access times as fast as 20ns are available. The IDT7198
offers a reduced power standby mode, ISB1, which is activated
when CS1 or CS2 goes HIGH. This capability decreases
power, while enhancing system reliability. The low-power
version (L) also offers a battery backup data retention capa-
bility where the circuit typically consumes only 30µW when
operating from a 2V battery.
All inputs and outputs are TTL-compatible and operate
from a single 5V supply.
The lDT7198 is packaged in either a 24-pin ceramic DlP,
28-pin leadless chip carrier, and 24-pin CERPACK.
Military grade product is manufactured in compliance with
the latest revision of MIL-STD-883, Class B, making it ideally
suited to military temperature applications demanding the
highest level of performance and reliability.
FUNCTIONAL BLOCK DIAGRAM
A0
DECODER
65,536-BIT
MEMORY ARRAY
VCC
GND
A13
I/O0
I/O1
I/O2
I/O3
INPUT
DATA
CONTROL
COLUMN I/O
CS1
CS2
WE1
OE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY TEMPERATURE RANGE
©1994 Integrated Device Technology, Inc.
6.4
2985 drw 01
MAY 1994
DSC-1027/4
1




IDT7198L85LB pdf, 반도체, 판매, 대치품
IDT7198S/L
CMOS STATIC RAM 64K (16K x 4-BIT) Added Chip Select and Output Enable Controls
MILITARY TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS(1)
(VCC = 5V ± 10%, VLC = 0.2V, VHC = VCC - 0.2V)
7198S20 7198S25 7198S35 7198S45 7198S55/70 7198S85
7198L20 7198L25 7198L35 7198L45 7198L55/70 7198L85
Symbol
Parameter
Power Military Military Military Military Military Military Unit
ICC1 Operating Power
Supply Current, CS1 and
CS2 VIL, Outputs Open
VCC = Max., f = 0(2)
S 105 105 105 105 105 105 mA
L 80 80 80 80 80 80
ICC2 Dynamic Operating
Current, CS1 and
CS2 VIL, Outputs Open
VCC = Max., f = fMAX(2)
S 160 155 140 140 140 140 mA
L 130 120 115 110 110 105
ISB Standby Power Supply
Current (TTL Level), CS1
or CS2 VIH, VCC = Max.,
Outputs Open, f = fMAX(2)
S 70 60 50 50 50 50 mA
L 50 40 35 35 35 35
ISB1 Full Standby Power
Supply Current (CMOS
Level) CS1 or CS2 VHC,
VCC= Max., VIN VHC or
VIN VLC, f = 0(2)
S 25 20 20 20 20 20
L 1.5 1.5 1.5 1.5 1.5 1.5
NOTES:
1. All values are maximum guaranteed values.
2. At f = fMAX address and data inputs are cycling at the maximum frequency of read cycles of 1/tRC. f = 0 means no input lines change.
mA
2985 tbl 06
DATA RETENTION CHARACTERISTICS OVER MILITARY TEMPERATURE RANGE
(L Version Only) VLC = 0.2V, VHC = VCC - 0.2V
Typ. (1)
VCC @
Max.
VCC @
Symbol
Parameter
Test Condition
Min.
2.0v
3.0V
2.0V
3.0V
VDR
ICCDR
tCDR(3)
tR(3)
|ILI|(3)
VCC for Data Retention
Data Retention Current
Chip Deselect to Data
Retention Time
Operation Recovery Time
Input Leakage Current
CS1 or CS2 VHC
VIN VHC or VLC
2.0
0
tRC(2)
10
———
15 600 900
———
———
—2
2
NOTES:
1. TA = +25°C.
2. tRC = Read Cycle Time.
3. This parameter is guaranteed by device characterization but is not production tested.
Unit
V
µA
ns
ns
µA
2985 tbl 09
LOW VCC DATA RETENTION WAVEFORM
DATA
RETENTION
MODE
VCC 4.5V
t CDR
VDR 2V
CS VIH VDR
4.5V
tR
VIH
2985 drw 04
6.4 4

4페이지










IDT7198L85LB 전자부품, 판매, 대치품
IDT7198S/L
CMOS STATIC RAMS 64K (16K x 4-BIT) Added Chip Select and Output Enable Controls
MILITARY TEMPERATURE RANGE
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED TIMING)(1, 2, 3, 7)
ADDRESS
tWC
OE
CS1, 2
WE
DATAOUT
DATAIN
tAW
tAS tWP (7) tWR
tWHZ (6)
(4)
tOW (6)
tDW tDH
DATA VALID
(4)
2985 drw 10
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CS CONTROLLED TIMING)(1)
tWC
ADDRESS
tAW
CS1, 2
tAS
tCW tWR
WE
DATAIN
tDW tDH
DATA VALID
2985 drw 11
NOTES:
1. WE, CS1 or CS2 must be HIGH during all address transitions.
2. A write occurs during the overlap (tWP) of a LOW WE, a LOW CS1 and a LOW CS2.
3. tWR is measured from the earlier of CS1, CS2 or WE going HIGH to the end of the write cycle.
4. During this period, the I/O pins are in the output state, and input signals must not be applied.
5. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, outputs remain in the high-impedance state.
6. Transition is measured ±200mV from steady state.
7. If OE is LOW during a WE controlled write cycle, the write pulse width must be the larger of tWP or (tWHZ + tDW) to allow the I/O drivers to turn off and data
to be placed on the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the write pulse can be as short
as the specified tWP.
6.4 7

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IDT7198L85LB

CMOS STATIC RAMs 64K (16K x 4-BIT) Added Chip Select and Output Controls

Integrated Device Technology
Integrated Device Technology

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