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PDF S3P7295 Data sheet ( Hoja de datos )
| Número de pieza | S3P7295 | |
| Descripción | The S3C7295 single-chip CMOS microcontroller has been designed for high performance using Samsungs newest 4-bit CPU core/ SAM47 (Samsung Arrangeable M | |
| Fabricantes | Samsung semiconductor | |
| Logotipo |  |
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S3C7295/P7295
1 PRODUCT OVERVIEW
PRODUCT OVERVIEW
OVERVIEW
The S3C7295 single-chip CMOS microcontroller has been designed for high performance using Samsung's
newest 4-bit CPU core, SAM47 (Samsung Arrangeable Microcontrollers).
With an up-to-704-dot LCD direct drive capability, and flexible 8-bit timer/counter, the S3C7295 offers an
excellent design solution for a mid-end LCD game.
Up to 8 pins of the 80-pin QFP package can be dedicated to I/O. Six vectored interrupts provide fast response to
internal and external events. In addition, the S3C7295's advanced CMOS technology provides for low power
consumption.
OTP
The S3C7295 microcontroller is also available in OTP (One Time Programmable) version, S3P7295. S3P7295
microcontroller has an on-chip 16K-byte one-time-programable EPROM instead of masked ROM.
The S3P7295 is comparable to S3C7295, both in function and in pin configuration.
1-1
1 page  
S3C7295/P7295
PRODUCT OVERVIEW
PIN DESCRIPTIONS
Table 1-1. S3C7295 Pin Descriptions
Pin Name
Pin
Type
Description
Circuit Number Share Pin
Type
P0.0
P0.1
P0.2
P0.3
I/O 4-bit I/O port.
1-bit and 4-bit read/write and test are possible.
Individual pins are software configurable as input or
output.
Individual pins are software configurable as open-
drain or push-pull output.
Individual pull-up resistors are software assignable;
pull-up resistors are automatically disabled for
output pins.
E-1
11 TCLO0/K0
10 TCLO0/K1
9 CLO/BUZ/K2
8 BUZ/K3
P1.0
P1.1
P1.2
P1.3
I/O Same as port 0.
E-1 7
6
5
4
INT0
INT1
INT2
INT4
INT0, INT1
I/O External interrupts. The triggering edge for INT0
and INT1 is selectable.
7, 6 P1.0, P1.1
INT2
I/O Quasi-interrupt with detection of rising or falling
edges
5 P1.2
INT4
I/O External interrupt with detection of rising or falling
edges.
4 P1.3
BUZ
I/O 2 kHz, 4 kHz, 8 kHz or 16 kHz frequency output for
buzzer sound.
8 P0.3/K3
BUZ
I/O Inverted BUZ signal
9 P0.2/CLO/K2
CLO
I/O Clock output
9 P0.2/BUZ/K2
TCLO0
I/O Inverted Timer/counter 0 clock output
10 P0.1/K1
TCLO0
I/O Timer/counter 0 clock output
11 P0.0/K0
COM0–COM15 O LCD common signal output
H-6 39–24
–
SEG0–SEG43 O LCD segment signal output
H-6 40–80,
1–3
–
1-5
5 Page 
ELECTRICAL DATA
S3C7295/P7295
Table 13-2. D.C. Electrical Characteristics (Concluded)
(TA = – 40 °C to + 85 °C, VDD = 2.2 V to 3.4 V)
Parameter
Supply
Current (1)
Symbol
Conditions
Min Typ Max Units
IDD1
VDD = 3V ± 10%
4.19 MHz (PCON=3H) crystal oscillator
C1 = C2 = 22 pF
– 1.3 3.0 mA
IDD2
Idle mode; VDD = 3 V ± 10%
4.19 MHz (PCON=3H) crystal oscillator
C1 = C2 = 22 pF
0.4 1.0
IDD3 (2) VDD = 3 V ± 10%
32 kHz crystal oscillator
– 15 30 µA
IDD4 (2) Idle mode; VDD = 3 V ± 10%
32 kHz crystal oscillator
5 15
IDD5 Stop mode; VDD = 3 V ± 10%
SCMOD=0000B,
XTin=0V
0.5 3
Stop mode; VDD = 3 V ± 10% SCMOD=0100B
0.2 2
NOTES:
1. Current in the following circuits are not included; on-chip pull-up resistors, internal LCD voltage dividing resistors,
voltage doubler, and output port drive currents.
2. Data includes power consumption for subsystem clock oscillation.
3. When the system clock control register, SCMOD, is set to 1001B, main system clock oscillation stops and the
subsystem clock is used.
13-4
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet S3P7295.PDF ] | |
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