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PDF S3P72P9 Data sheet ( Hoja de datos )
| Número de pieza | S3P72P9 | |
| Descripción | SINGLE-CHIP MICROCONTROLLER HAS BEEN DESIGNED FOR HIGH PERFORMANCE USING | |
| Fabricantes | Samsung semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de S3P72P9 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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S3C72P9/P72P9 (Preliminary Spec)
PRODUCT OVERVIEW
1 PRODUCT OVERVIEW
OVERVIEW
The S3C72P9 single-chip CMOS microcontroller has been designed for high performance using Samsung's
newest 4-bit CPU core, SAM47 (Samsung Arrangeable Microcontrollers).
With an up-to-896-dot LCD direct drive capability, flexible 8-bit and 16-bit timer/counters, and serial I/O interface,
the S3C72P9 offers an excellent design solution for a wide variety of applications which require LCD functions.
Up to 39 pins of the 100-pin QFP package can be dedicated to I/O. Eight vectored interrupts provide fast
response to internal and external events. In addition, the S3C72P9's advanced CMOS technology provides for
low power consumption and a wide operating voltage range.
The S3C72P9 is made by shrinking the KS57C21516. The S3C72P9 is comparable to KS57C21516, both in
function and in pin configuration except that S3C72P9 have a 32,768 ×8-bit ROM, 1056×4-bit RAM, 12 common
selectable and LCD contrast control function.
OTP
The S3C72P9 microcontroller is also available in OTP (One Time Programmable) version, S3P72P9. S3P72P9
microcontroller has an on-chip 32K-byte one-time-programmable EPROM instead of masked ROM. The
S3P72P9 is comparable to S3C72P9, both in function and in pin configuration.
1–1
1 page  
S3C72P9/P72P9 (Preliminary Spec)
PRODUCT OVERVIEW
PIN DESCRIPTIONS
Pin Name
P0.0
P0.1
P0.2
P0.3
P1.0
P1.1
P1.2
P1.3
P2.0
P2.1
P2.2
P3.0
P3.1
P3.2
P3.3
P4.0–P4.3
P5.0–P5.3
P6.0–P6.3
P7.0–P7.3
P8.0–P8.3
P9.0–P9.3
SCK
SO
SI
BUZ
INT0, INT1
Pin Type
I/O
I
I/O
I/O
I/O
I/O
Table 1-1. S3C72P9/P72P9 Pin Descriptions
Description
Number
4-bit I/O port.
1-bit and 4-bit read/write and test are possible.
Individual pins are software configurable as input or
output.
Individual pins are software configurable as open-
drain or push-pull output.
4-bit pull-up resistors are software assignable; pull-up
resistors are automatically disabled for output pins.
11
12
13
14
4-bit input port.
1-bit and 4-bit read and test are possible.
4-bit pull-up resistors are assignable by software.
23
24
25
26
Same as port 0 except that port 2 is 3-bit I/O port.
27
28
29
Same as port 0.
30
31
32
33
4-bit I/O ports.
1-, 4-bit or 8-bit read/write and test are possible.
Individual pins are software configurable as input or
output.
4-bit pull-up resistors are software assignable; pull-up
resistors are automatically disabled for output pins.
42–45
46–49
Same as P4, P5.
50–53
Share Pin
SCK/K0
SO/K1
SI/K2
BUZ/K3
INT0
INT1
INT2
INT4
CLO
LCDCK
LCDSY
TCLO0
TCLO1
TCL0
TCL1
COM8–
COM11
COM12–
COM15
SEG55/K4–
SEG52/K7
I/O Same as P4, P5.
I/O Serial I/O interface clock signal.
54–57
58–61
62–65
11
SEG51–
SEG48
SEG47–
SEG44
SEG43–
SEG40
P0.0/K0
I/O Serial data output.
12 P0.1/K1
I/O Serial data input.
13 P0.2/K2
I/O 2 kHz, 4 kHz, 8 kHz or 16 kHz frequency output for
buzzer signal.
14
P0.3/K3
I External interrupts. The triggering edge for INT0 and 23, 24 P1.0, P1.1
INT1 is selectable.
1–5
5 Page 
S3C72P9/P72P9 (Preliminary Spec)
PRODUCT OVERVIEW
VDD
VLC1
COM
VLC4
VLC5
Out
Figure 1-10. Pin Circuit Type H-3
Pull-up
Resistor
Enable
COM/SEG
Output
Disable
Data
VDD
Pull-up
Resistor
P-CH
Type H-3
Type C
I/O
Figure 1-11. Pin Circuit Type H-13
1–11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet S3P72P9.PDF ] | |
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