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S42WD61SBP 데이터시트 PDF




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부품번호 S42WD61SBP 기능
기능 Dual Voltage Supervisory Circuit With Watchdog Timer
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S42WD61SBP 데이터시트, 핀배열, 회로
S4242/S42WD42/S4261/S42WD61
Dual Voltage Supervisory Circuit
With Watchdog Timer(S42WD61) (S42WD42)
FEATURES
• Precision Dual Voltage Monitor
– VCC Supply Monitor
- Dual reset outputs for complex
microcontroller systems
- Integrated memory write lockout function
- No external components required
• Second Voltage Monitor Output
– Separate VLOW output
– Generates interrupt to MCU
– Generates RESET for dual supply systems
- Guaranteed output assertion to VCC - 1V
• Watchdog Timer (S42WD42, S42WD61)
– 1.6s
• Memory Internally Organized 2 x8
• Extended Programmable Functions
Available on SMS24
• High Reliability
– Endurance: 100,000 erase/write cycles
– Data retention: 100 years
OVERVIEW
The S42xxx are a precision power supervisory circuit. It
automatically monitors the device’s VCC level and will
generate a reset output on two complementary open drain
outputs. In addition to the VCC monitoring, the S42xxx also
provides a second voltage comparator input. This input
has an independent open drain output that can be wire-
OR’ed with the RESET I/O or it can be used as a system
interrupt.
The S42xxx also has an integrated 4k/16k-bit nonvolatile
memory. The memory conforms to the industry standard
two-wire serial interface. In addition to the reset circuitry,
the S42WD42/S42WD61 also has a watchdog timer.
BLOCK DIAGRAM
VCC
8
SCL 6
SDA 5
NONVOLATILE
MEMORY
ARRAY
WRITE
CONTROL
PROGRAMMABLE
RESET PULSE
GENERATOR
2 RESET#
+
VSENSE 3
1.26V
4
GND
+
VTRIP
RESET
CONTROL
PROGRAMMABLE
WATCHDOG
TIMER
(S42WD42,
S42WD61)
UV
OV
2025 T BD 2.0
7 RESET
1 VLOW#
SUMMIT MICROELECTRONICS, Inc. • 300 Orchard City Drive, Suite 131 • Campbell, CA 95008 • Telephone 408-378-6461 • Fax 408-378-6586 • www.summitmicro.com
© SUMMIT MICROELECTRONICS, Inc. 2000
2025 6.0 4/17/00
Characteristics subject to change without notice
1




S42WD61SBP pdf, 반도체, 판매, 대치품
VCC
VTRIP
VRVALID
RESET#
RESET
S4242/S42WD42/S4261/S42WD61
tGLITCH
tPURST
tRPD
tPURST
FIGURE 3. RESET OUTPUT TIMING
tRPD
2025 T fig03 2.0
RESET CIRCUIT AC and DC ELECTRICAL CHARACTERISTICS
TA=-40°C to +85°C
Symbol
Parameter
Part no.
Suffix
VTRIP
Reset Trip Point
A (or) Blank
B
2.7
tPURST
Reset Timeout
tRPD
VTRIP to RESET Output Delay
VRVALID
RESET Output Valid to VCC min. Guarantee
tGLITCH
Glitch Reject Pulse Width note 1
VOLRS
RESET Output Low Voltage IOL = 1mA
VOHRS
RESET High Voltage Output IOH = 800µA
VULH
VSENSE Under-voltage threshold low to high
VUHL
VSENSE Under-voltage threshold high to low
VOLH
VSENSE Over-voltage threshold low to high
VOHL
VSENSE Over-voltage threshold high to low
tVD1 Delay to VLOW Active
tVD2 Delay to VLOW Released
tWDTO
Watchdog timeout Period (S42WD61)
(S42WD42)
Min.
4.250
4.50
2.7
1
VCC-.75
1.20
1.20
1.20
1.20
Typ.
4.375
4.625
2.9
200
30
1.25
1.25
1.25
1.25
1600
Max.
4.5
4.75
3.10
5
0.4
1.30
1.30
1.30
1.30
5
5
Unit
V
V
V
ms
µs
V
ns
V
V
V
V
V
V
µs
µs
ms
2025 PGM T5.2
2025 6.0 4/17/00
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S42WD61SBP 전자부품, 판매, 대치품
S4242/S42WD42/S4261/S42WD61
PIN DESCRIPTIONS
ENDURANCE AND DATA RETENTION
Serial Clock (SCL) - The SCL input is used to clock data
into and out of the device. In the WRITE mode, data must
remain stable while SCL is HIGH. In the READ mode, data
is clocked out on the falling edge of SCL.
Serial Data (SDA) - The SDA pin is a bidirectional pin
used to transfer data into and out of the device. Data may
change only when SCL is LOW, except START and STOP
conditions. It is an open-drain output and may be wire-
ORed with any number of open-drain or open-collector
outputs.
RESET# - RESET# is an active low open-drain output. It
should be tied high through a pull-up resistor connected to
VCC. RESET# is an I/O, therefore it may also be used to
condition a RESET# signal generated by another device;
it can also be used to debounce a pushbutton input.
RESET - RESET is an active high open drain (PFET)
output. It should be tied low through a pull-down resistor
connected to ground. RESET is an I/O, therefore it may
also be used to condition a RESET signal generated by
another device.
VSENSE - The VSENSE input is used as a second voltage
sensing input. The pin is tied to a comparator that uses the
precision internal 1.25V reference.
VLOW# - VLOW# is an active low open drain output driven
low whenever VSENSE is below 1.25V. It is not a timed
output and only responds to the state of VSENSE.
The S42xxx is designed for applications requiring
100,000 erase/write cycles and unlimited read cycles. It
provides 100 years of secure data retention, with or
without power applied, after the execution of 100,000
erase/write cycles.
Reset Controller Description
The S42xxx provides a precision RESET controller that
ensures correct system operation during brown-out and
power-up/-down conditions. It is configured with two open
drain RESET outputs; pin 7 is an active high output and
pin 2 is an active low output. For proper operation pin 7
should be tied low through a pull-down resistor while pin
2 should be tied high through a resistor connected to VCC.
During power-up, the RESET outputs remain active until
VCC reaches the VTRIP threshold and will continue driving
the outputs for tPURST (200 msec)after reaching VTRIP.
The RESET outputs will be valid so long as VCC is > 1.0V.
During power-down, the RESET outputs will begin driving
active when VCC falls below VTRIP.
The RESET pins are I/Os; therefore, the S42xxx can act
as a signal conditioning circuit for an externally applied
reset. The inputs are edge triggered; that is, the RESET
input will initiate a reset timeout after detecting a low to
high transition and the RESET# input will initiate a reset
timeout after detecting a high to low transition. Refer to the
applications information section for more details on de-
vice operation as a reset conditioning circuit.
Voltage Sensor Description
VSENSE is an auxiliary voltage detection circuit. Its thresh-
old is set at 1.25V and it generates a VLOW# output for an
under-voltage condition. Because the VLOW# output is
open-drain, it can be wire-ORed with the RESET# output
or tied directly to an IRQ input on a microcontroller.
2025 6.0 4/17/00
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